Booting method of computing system including memory module with processing device mounted

Patent metadata

Field	Value
Publication number	US-11620135-B2
Application number	US-202017115924-A
Country	US
Kind code	B2
Filing date	Dec 9, 2020
Priority date	May 7, 2020
Publication date	Apr 4, 2023
Grant date	Apr 4, 2023

Abstract

A booting method of a computing system, which includes a memory module including a processing device connected to a plurality of memory devices, including: powering up the computing system; after powering up the computing system, performing first memory training on the plurality of memory devices by the processing device in the memory module, and generating a module ready signal indicating completion of the first memory training; after powering up the computing system, performing a first booting sequence by a host device, the host device executing basic input/output system (BIOS) code of a BIOS memory included in the computing system; waiting for the module ready signal to be received from the memory module in the host device after performing the first booting sequence; and receiving the module ready signal in the host device, and performing a second booting sequence based on the module ready signal.

First claim

What is claimed is:

1. A memory module, comprising:
a printed circuit board;
a plurality of memory devices coupled to the printed circuit board; and
a processing device coupled to the printed circuit board and connected to the plurality of memory devices,
wherein the processing device is configured to:
after the memory module is powered-up, perform first memory training on the plurality of memory devices,

generate a module ready signal that indicates completion of the first memory training, after completing the first memory training, and
transmit the module ready signal to a host device that is outside of the memory module, the module ready signal causing the host device to perform a second booting operation after the host device performs a first booting operation, the first booting operation including executing basic input/output system (BIOS) code of a BIOS memory.

2. The memory module as claimed in claim 1 , wherein the module ready signal is output to the outside of the memory module through unused pins among connecting pins of the memory module.

3. The memory module as claimed in claim 1 , wherein the module ready signal is output to the outside of the memory module through a pin dedicated to the module ready signal among connecting pins of the memory module.

4. The memory module as claimed in claim 1 , wherein:
the processing device includes a memory controller that controls the first memory training for the plurality of memory devices, and
the memory controller performs the first memory training using a training circuitry and generates the module ready signal.

5. The memory module as claimed in claim 1 , wherein the memory module is a dual in-line memory module.

6. A computing system, comprising:
a board;
a host device mounted on the board;
a memory module mounted on the board and connected to the host device, the memory module including a plurality of memory devices and a processing device connected to the plurality of memory devices; and
a basic input/output system (BIOS) memory configured to store BIOS code for booting the computing system, wherein:
the processing device is configured to, after the computing system is powered up:
perform first memory training on the plurality of memory devices, and
generate a module ready signal that indicates completion of the first memory training, after completing the first memory training, and transmit the module ready signal to the host device, and

the host device is configured to, after the computing system is powered up:
perform a first booting sequence that includes executing the BIOS code of the BIOS memory,
after performing the first booting sequence, wait for the module ready signal to be received from the memory module, and
perform a second booting operation in response to receiving the module ready signal from the memory module.

7. The computing system as claimed in claim 6 , wherein the memory module outputs the module ready signal to the outside of the memory module through an unused pin among connecting pins of the memory module.

8. The computing system as claimed in claim 6 , wherein the memory module outputs the module ready signal to the outside of the memory module through a pin dedicated to the module ready signal among connecting pins of the memory module.

9. The computing system as claimed in claim 6 , wherein the module ready signal is transmitted to the host device through an interrupt signal line formed on the board.

10. The computing system as claimed in claim 6 , wherein the module ready signal is transmitted to the host device through a module ready signal line formed on the board.

11. A booting method of a computing system that includes a memory module including a processing device connected to a plurality of memory devices, the method comprising:
powering up the computing system;
after powering up the computing system, performing first memory training on the plurality of memory devices by the processing device in the memory module, and generating a module ready signal indicating completion of the first memory training;
after powering up the computing system, performing a first booting sequence by a host device, the host device executing basic input/output system (BIOS) code of a BIOS memory included in the computing system;
waiting for the module ready signal to be received from the memory module in the host device after performing the first booting sequence; and
receiving the module ready signal in the host device, and performing a second booting sequence based on the module ready signal.

12. The method as claimed in claim 11 , wherein the performing of the first memory training and the performing of the first booting sequence are performed in parallel.

13. The method as claimed in claim 11 , wherein:
the first booting sequence is configured to read ID information on hardware components of the computing system, and
the first booting sequence includes checking a type and memory attribute of the memory module from a serial presence detect memory of the memory module.

14. The method as claimed in claim 13 , wherein the memory module is a dual in-line memory module.

15. The method as claimed in claim 11 , wherein the second booting sequence includes performing second memory training on the plurality of memory devices of the memory module by the host device.

16. The method as claimed in claim 15 , wherein the second memory training performed by the host device is configured to perform transparently for the processing device.

17. The method as claimed in claim 11 , further comprising, after performing the first memory training, outputting the module ready signal from the memory module to the outside of the memory module through an unused pin among connecting pins of the memory module.

18. The method as claimed in claim 11 , further comprising, after performing the first memory training, outputting the module ready signal from the memory module to the outside of the memory module through a pin dedicated to the module ready signal among connecting pins of the memory module.

19. The method as claimed in claim 11 , further comprising transmitting the module ready signal to the host device through an interrupt signal line formed on a board of the computing system.

20. The method as claimed in claim 11 , further comprising transmitting the module ready signal to the host device through a module ready signal line formed on a board of the computing system.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Lee Jonggeon
• Kim Kyungsoo
• So Jinin
• Kwon Yongsuk
• Jung Jin
• Cho Jeonghyeon

Classifications

• G11C29/028

  with adaption or trimming of parameters · CPC title

• G06F11/27

  Built-in tests · CPC title

• G06N20/00

  Machine learning · CPC title

• G11C29/12

  Built-in arrangements for testing, e.g. built-in self testing [BIST] {or interconnection details} · CPC title

• G11C7/20

  Memory cell initialisation circuits, e.g. when powering up or down, memory clear, latent image memory · CPC title