Integrated circuit with self-test circuit, method for operating an integrated circuit with self-test circuit, multi-core processor device and method for operating a multi-core processor device

Patent metadata

Field	Value
Publication number	US-11619668-B2
Application number	US-202117179955-A
Country	US
Kind code	B2
Filing date	Feb 19, 2021
Priority date	Feb 21, 2020
Publication date	Apr 4, 2023
Grant date	Apr 4, 2023

Abstract

An integrated circuit with self-test circuit is provided. The integrated circuit includes at least one logic circuit, at least one input storage element for storing work data, at least one output storage element, an input test storage element for storing test data, and at least one output test storage element, wherein the logic circuit is selectively connected to the input storage element on the input side, such that the input storage element provides the work data to the logic circuit, or is connected to the input test storage element on the input side, such that the input test storage element provides the test data to the logic circuit, wherein the logic circuit is further connected to the output storage element and the output test storage element on the output side, such that the logic circuit feeds data to the output storage element and/or to the output test storage element, and wherein the output storage element is configured to process the data from the logic circuit if the work data are provided to the logic circuit, and not to process the data from the logic circuit if the test data are provided to the logic circuit.

First claim

What is claimed is:

1. An integrated circuit with self-test circuit, comprising:
at least one logic circuit;
at least one input storage element for storing work data;
at least one output storage element;
at least one input test storage element for storing test data; and
at least one output test storage element;
wherein the logic circuit is selectively connected to the input storage element on an input side of the logic circuit, such that the input storage element is connected to the logic circuit, and provides the work data to the logic circuit in a work mode, or
is selectively connected to the input test storage element on the input side of the logic circuit, such that the input test storage element is connected to the logic circuit, and provides the test data to the logic circuit in a test mode;
circuitry configured to load the test data into the input test storage element while the logic circuit is connected to the input storage element and the output storage element;
wherein the logic circuit is furthermore connected or selectively connected to both the output storage element and the output test storage element on an output side of the logic circuit, such that when the logic circuit is connected to the output storage element the logic circuit feeds data to the output storage element, and when the logic circuit is connected to the output test storage element the logic circuit feeds data to the output test storage element, and when the logic circuit is connected to both the output storage element and to the output test storage element the logic circuit feeds data to both the output storage element and the output test storage element;
wherein the output storage element is configured to process the data from the logic circuit when the work data are provided to the logic circuit in the work mode, and not to process the data from the logic circuit when the test data are provided to the logic circuit in the test mode.

2. The integrated circuit as claimed in claim 1 , further comprising:
a controller configured to switch over between:
the connection of the input side of the logic circuit to the input storage element and an activation of the output storage element, such that the output storage element processes the work data fed thereto; and
the connection of the input side of the logic circuit to the input test storage element and a deactivation of the output storage element, such that the work data fed to the output storage element are ignored, or vice versa.

3. The integrated circuit as claimed in claim 2 ,
wherein the controller comprises a multiplexer.

4. The integrated circuit as claimed in claim 3 , wherein the controller is configured to:
provide a switching signal having a first signal value for the purpose of connecting the input side of the logic circuit to the input storage element and activating the output storage element; and
provide the switching signal having a second signal value for the purpose of connecting the logic circuit to the input side of the input test storage element and deactivating the output storage element, and
wherein the multiplexer has a control input and the controller is configured to provide the switching signal to the control input of the multiplexer.

5. The integrated circuit as claimed in claim 2 , wherein the controller is configured to:
provide a switching signal having a first signal value for the purpose of connecting the input side of the logic circuit to the input storage element and activating the output storage element; and
provide the switching signal having a second signal value for the purpose of connecting the logic circuit to the input side of the input test storage element and deactivating the output storage element.

6. The integrated circuit as claimed in claim 5 ,
wherein the controller is further configured to provide the switching signal at least to a multiplexer and to the output storage element.

7. The integrated circuit as claimed in claim 5 ,
wherein the input storage element, the output storage element, the input test storage element and the output test storage element each comprises at least one flip-flop,
wherein the at least one flip-flop of the output storage element has an enable input and/or a clock enable input, and
wherein the controller is further configured to provide the switching signal to the enable input or to the clock enable input.

8. The integrated circuit as claimed in claim 1 ,
wherein the input storage element, the output storage element, the input test storage element and the output test storage element each comprises at least one flip-flop.

9. The integrated circuit as claimed in claim 1 ,
wherein the input test storage element is configured to form in the work mode an input safety storage element configured to redundantly store the data stored in the input storage element prior to transfer of the data to the logic circuit, and/or
wherein the output test storage element is configured to form in the work mode an output safety storage element configured to redundantly store the data stored in the output storage element after transfer of the data from the logic circuit.

10. The integrated circuit as claimed in claim 1 , further comprising:
at least one additional output storage element; and
at least one additional output test storage element,
wherein the at least one logic circuit comprises a plurality of logic circuits, and
wherein during the connection of the logic circuit to the input test storage element and the output test storage element the plurality of logic circuits together with the input test storage element, the output test storage element and the at least one additional output test storage element forms a scan chain,
wherein the at least one additional output storage element is not part of the scan chain.

11. The integrated circuit as claimed in claim 10 ,
wherein the logic circuit connected to the input test storage element and to the output test storage element forms, together with the input test storage element and the output test storage element, a first chain link of the scan chain, and
wherein each additional chain link of the scan chain comprises one of the plurality of logic circuits, which is connected to the output test storage element of the preceding chain link on the input side and is connected to a further output test storage element on the output side.

12. The integrated circuit as claimed in claim 11 ,
wherein the output test storage element of a preceding chain link provides to each of the logic circuits of the additional chain links the test data processed by the logic circuit of the preceding chain link, and
wherein each of the logic circuits of the additional chain links feeds the test data processed by it to the output test storage element on the output side.

13. A method for operating an integrated circuit with self-test circuit, said integrated circuit comprising at least one logic circuit, at least one input storage element for storing work data, at least one output storage element, at least one input test storage element for storing test data and at least one output test storage element, wherein the logic circuit is selectively connected to the output storage element and to an output test storage element on the output side of the logic circuit, the method comprising:
when the logic circuit is connected to the input storage element on an input side of the logic circuit:
providing the work data to the logic circuit by means of the input storage element,
feeding the work data processed by the logic circuit to the output storage element, and
processing the work data from the logic circuit in

Assignees

• Infineon Technologies Ag

Inventors

• Tille Daniel
• Ahrens Heiko
• Rosenbusch Jens

Classifications

• G01R31/31713

  Input or output interfaces for test, e.g. test pins, buffers (for scan test G01R31/318572) · CPC title

• G01R31/318572

  Input/Output interfaces · CPC title

• G11C29/12

  Built-in arrangements for testing, e.g. built-in self testing [BIST] {or interconnection details} · CPC title

• G01R31/318536

  Scan chain arrangements, e.g. connections, test bus, analog signals · CPC title

• G01R31/318541

  Scan latches or cell details · CPC title