Method for managing the operation of a test mode of a logic component with restoration of the pre-test state

Patent metadata

Field	Value
Publication number	US-2017205461-A1
Application number	US-201515324851-A
Country	US
Kind code	A1
Filing date	May 28, 2015
Priority date	Jul 9, 2014
Publication date	Jul 20, 2017
Grant date	—

Abstract

A device may include a control circuit configured to place, after a normal mode operation of N flip-flops, the N flip-flops in a test mode in which the test input of the first flip-flop of the chain is intended to receive a first sequence of test bits. A memory may be configured to store a sequence of N values delivered by the test output of the last flip-flop of the chain. The control circuit may be configured to deliver, at the test input of the first flip-flop of the chain, the sequence of N stored values to restore the state of the N flip-flops before their placement in the test mode.

First claim

1 - 6 . (canceled)

7 . A method for operating a plurality of flip-flops in an integrated circuit, each flip-flop having a test output and a test input, and the plurality of flip-flops being coupled together in series via their test outputs and test inputs, the method comprising:
following a normal mode of operation of the plurality of flip-flops when the flip-flops are in an initial state, placing the plurality of flip-flops in a test mode by inputting a first sequence of N test bits into the test input of the first flip-flop of the series; storing a sequence of N values output by the test output of the last flip-flop of the series resulting from inputting the first sequence of N test bits; and inputting the sequence of N stored values into the test input of the first flip-flop of the series after the test mode to restore the flip-flops to their initial state prior to placement in the test mode.

8 . The method of claim 7 wherein the test mode further comprises at least one second sequence of N test bits following the first sequence of N test bits.

9 . The method of claim 7 wherein inputting the sequence of N stored values comprises inputting the sequence of N stored values following inputing of a last bit of the sequence of N test bits.

10 . An electronic device comprising:
an integrated circuit comprising a plurality of flip-flops, each flip-flop having a test output and a test input, and the plurality of flip-flops being coupled together in series via their test outputs and test inputs; a controller configured to place the plurality of flip-flops in a test mode following a normal mode of operation when the flip-flops are in an initial state by inputting a first sequence of N test bits into the test input of the first flip-flop of the series; and a storage device configured to store a sequence of N values output by the test output of the last flip-flop of the series resulting from inputting the first sequence of N test bits; said controller is configured to input the sequence of N stored values into the test input of the first flip-flop of the series after the test mode to restore the flip-flops to their initial state prior to placement in the test mode.

11 . The electronic device of claim 10 wherein the storage device comprises a random access memory external to the integrated circuit.

12 . The electronic device of claim 11 further comprising a substrate upon which the integrated circuit and the random access memory are mounted.

13 . The electronic device of claim 10 wherein the test mode further comprises at least one second sequence of N test bits following the first sequence of N test bits.

14 . The electronic device of claim 10 wherein the controller inputs the sequence of N stored values following inputting of a last bit of the sequence of N test bits.

15 . A device for testing an integrated circuit comprising a plurality of flip-flops, each flip-flop having a test output and a test input, and the plurality of flip-flops being coupled together in series via their test outputs and test inputs, the device comprising:
a controller configured to place the plurality of flip-flops in a test mode following a normal mode of operation when the flip-flops are in an initial state by inputting a first sequence of N test bits into the test input of the first flip-flop of the series; and a storage device configured to store a sequence of N values output by the test output of the last flip-flop of the series resulting from inputting the first sequence of N test bits; wherein the controller is further configured to input the sequence of N stored values into the test input of the first flip-flop of the series after the test mode to restore the flip-flops to their initial state prior to placement in the test mode.

16 . The device of claim 15 wherein the storage device comprises a random access memory external to the integrated circuit.

17 . The device of claim 16 further comprising a substrate upon which the integrated circuit and the random access memory are mounted.

18 . The device of claim 15 wherein the test mode further comprises at least one second sequence of N test bits following the first sequence of N test bits.

19 . The device of claim 15 wherein the controller inputs the sequence of N stored values following inputting of a last bit of the sequence of N test bits.

Assignees

• Stmicroelectronics (Grenoble 2) Sas
• St Microelectronics Crolles 2 Sas

Inventors

• Daveau Jean-Marc
• Roche Philippe
• Fuin Didier

Classifications

• G01R31/318555 Primary

  Control logic · CPC title

• G01R31/3177 Primary

  Testing of logic operation, e.g. by logic analysers · CPC title

• G01R31/31701

  Arrangements for setting the Unit Under Test [UUT] in a test mode · CPC title

• G01R31/31723

  Hardware for routing the test signal within the device under test to the circuits to be tested, e.g. multiplexer for multiple core testing, accessing internal nodes (routing the test signal to or from the device under test G01R31/31926) · CPC title

• G01R31/31724

  Test controller, e.g. BIST state machine (for scan test G01R31/318555) · CPC title