Electronic package

Patent metadata

Field	Value
Publication number	US-11616007-B2
Application number	US-202017066411-A
Country	US
Kind code	B2
Filing date	Oct 8, 2020
Priority date	Oct 8, 2020
Publication date	Mar 28, 2023
Grant date	Mar 28, 2023

Abstract

An electronic package and method for manufacturing the same are provided. The electronic package includes a substrate and a wetting layer. The substrate includes a plurality of conductive step structures each including a first portion and a second portion. The first portion has a first bottom surface, a first outer surface and a first inner surface. The second portion has a second bottom surface, a second outer surface and a second inner surface, wherein the second portion partially exposes the first bottom surface. The wetting layer at least covers the second bottom surface, the second outer surface and the second inner surface of the second portion of each of the conductive step structures.

First claim

What is claimed is:

1. An electronic package, comprising:
a substrate comprising a plurality of conductive step structures each including a first portion and a second portion, the first portion having a first bottom surface, a first outer surface and a first inner surface, and the second portion having a second bottom surface, a second outer surface and a second inner surface, wherein the second portion partially exposes the first bottom surface; and
a wetting layer at least covering the second bottom surface, the second outer surface and the second inner surface of the second portion of each of the conductive step structures;
wherein the substrate further comprises a circuit layer electrically connected to the conductive step structures;
wherein the conductive step structures define a cavity on a bottom surface of the substrate, and a portion of the circuit layer is exposed from the bottom surface of the substrate.

2. The electronic package according to claim 1 , wherein the wetting layer exposes the first outer surface and the first inner surface.

3. The electronic package according to claim 1 , wherein the wetting layer further directly contact a portion of the first bottom surface.

4. The electronic package according to claim 1 , wherein the wetting layer comprises a multi-layered wetting layer including a first wetting layer and a second wetting layer.

5. The electronic package according to claim 4 , wherein the first wetting layer covers at least a portion of the first bottom surface, and the second bottom surface, the second outer surface and the second inner surface.

6. The electronic package according to claim 5 , wherein the second wetting layer covers the second outer surface and a portion of the first bottom surface.

7. The electronic package according to claim 6 , wherein the second wetting layer further covers the second bottom surface.

8. The electronic package according to claim 1 , wherein a portion of the circuit layer is exposed from a front surface of the substrate.

9. The electronic package according to claim 8 , further comprising a first encapsulant disposed on the front surface of the substrate.

10. The electronic package according to claim 1 , further comprising at least one electronic component disposed on the bottom surface of the substrate in the cavity, and electrically connected to the circuit layer.

11. The electronic package according to claim 10 , further comprising a second encapsulant disposed on the bottom surface of the substrate and encapsulating the at least one electronic component.

12. The electronic package according to claim 1 , wherein the first portion and the second portion of each of the plurality of conductive step structures are in direct contact with each other with an interface therebetween.

13. An electronic package, comprising:
a substrate comprising a circuit layer including a stack of a first conductive layer and a second conductive layer, wherein the first conductive layer includes a first bottom surface and a first outer surface, the second conductive layer includes a second bottom surface and a second outer surface, the second conductive layer exposing a portion of the first bottom surface of the first conductive layer, thereby defining a conductive step structure,
wherein the second outer surface and the second bottom surface form a conductive path;
wherein the conductive step structure defines a cavity on a bottom surface of the substrate, and a portion of the circuit layer is exposed from the bottom surface of the substrate.

14. The electronic package according to claim 13 , further comprising a wetting layer covering the second outer surface, the second bottom surface and a second inner surface of the second conductive layer.

15. The electronic package according to claim 13 , wherein the first conductive layer and the second conductive layer are in direct contact with each other with an interface therebetween.

16. The electronic package according to claim 11 , further comprising an electronic component disposed on a front surface of the substrate and electrically connected to the circuit layer.

17. An electronic package, comprising:
a substrate comprising a circuit layer including a stack of a first conductive layer and a second conductive layer, wherein the first conductive layer includes a first bottom surface and a first outer surface, the second conductive layer includes a second bottom surface and a second outer surface, the second conductive layer exposing a portion of the first bottom surface of the first conductive layer, thereby defining a conductive step structure,
wherein the second outer surface and the first bottom surface form a conductive path;
wherein the conductive step structure defines a cavity on a bottom surface of the substrate, and a portion of the circuit layer is exposed from the bottom surface of the substrate.

18. The electronic package according to claim 17 , wherein the conductive path further consisting of the second outer surface, the first bottom surface and the second bottom surface.

Assignees

• Advanced Semiconductor Eng

Inventors

• Yen You-Lung
• Appelt Bernd Karl
• Essig Kay Stephan

Classifications

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W70/60

  Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40) · CPC title

• H10W90/22

  the stacked chips being on both top and bottom sides of a package substrate, interposer or RDL · CPC title

• H10W72/0198

  batch processes · CPC title

• H10W90/722

  between stacked chips · CPC title