Semiconductor structure and method for forming the same

Patent metadata

Field	Value
Publication number	US-11615983-B2
Application number	US-202117166539-A
Country	US
Kind code	B2
Filing date	Feb 3, 2021
Priority date	Apr 22, 2020
Publication date	Mar 28, 2023
Grant date	Mar 28, 2023

Abstract

A semiconductor interconnect structure includes a conductive line electrically coupled to an active semiconductor device, a first etch stop layer formed over the conductive line, a first dielectric layer formed over the first etch stop layer, a second etch stop layer formed over the first dielectric layer, a second dielectric layer formed over the second etch stop layer, and an interconnect structure electrically coupled to the conductive line and extending through the first etch stop layer, the first dielectric layer, the second etch stop layer, and the second dielectric layer. The interconnect structure includes a via extending through the first etch stop layer, the second etch stop layer, and the first dielectric layer and a trench extending through the second dielectric layer.

First claim

What is claimed is:

1. A semiconductor structure, comprising:
a conductive line;
a first etch stop layer formed over the conductive line;
a first dielectric layer formed over the first etch stop layer;
a second etch stop layer formed over the first dielectric layer;
a second dielectric layer formed over the second etch stop layer;
an interconnect structure electrically coupled to the conductive line and extending through the first etch stop layer, the first dielectric layer, the second etch stop layer, and the second dielectric layer, the interconnect structure comprising:
a via extending through the first etch stop layer, the second etch stop layer, and the first dielectric layer; and
a trench extending through the second dielectric layer; and

an insulating layer formed between the second etch stop layer and the second dielectric layer, wherein a junction of the via and the trench is aligned with an interface between the second etch stop layer and the insulating layer.

2. The semiconductor structure of claim 1 , wherein the second etch stop layer surrounds a junction of the via and the trench.

3. The semiconductor structure of claim 1 , wherein the insulating layer is formed of silicon oxide.

4. The semiconductor structure of claim 1 , wherein the second etch stop layer is formed using aluminum oxide.

5. The semiconductor structure of claim 1 , wherein a width of the via ranges from 5 nanometers to 15 nanometers.

6. The semiconductor structure of claim 1 , wherein a width of the trench ranges from 15 nanometers to 20 nanometers.

7. The semiconductor structure of claim 1 , wherein a thickness of the second etch stop layer ranges from 10 angstroms to 30 angstroms.

8. A method of fabricating a semiconductor structure, comprising:
forming a first etch stop layer over a conductive line;
forming a first dielectric layer over the first etch stop layer;
forming a second etch stop layer over the first dielectric layer;
forming an insulating layer over the second etch stop layer;
removing a portion of the second etch stop layer to expose a portion of the first dielectric layer;
forming a second dielectric layer over the second etch stop layer and the first dielectric layer;
removing a portion of the second dielectric layer, a portion of the first dielectric layer, and a portion of the first etch stop layer to form an opening and expose the conductive line; and
filling the opening with conductive material to form a via and a trench, wherein a junction of the via and the trench is aligned with an interface between the second etch stop layer and the insulating layer.

9. The method of claim 8 , wherein the insulating layer is formed of silicon oxide.

10. The method of claim 8 , wherein removing a portion of the second dielectric layer, a portion of the first dielectric layer, and a portion of the first etch stop layer to form the opening further comprises removing a portion of the insulating layer to form the opening.

11. The method of claim 8 , further comprising applying a photoresist over the insulating layer before removing the portion of the second etch stop layer to expose the portion of the first dielectric layer.

12. The method of claim 8 , further comprising applying a photoresist over the second etch stop layer before removing the portion of the second etch stop layer to expose the portion of the first dielectric layer.

13. The method of claim 8 , further comprising forming a third etch stop layer over the second dielectric layer and the conductive material.

14. A method of fabricating a semiconductor structure, comprising:
forming a first etch stop layer over a conductive line that is electrically coupled to an active semiconductor device;
forming a first dielectric layer over the first etch stop layer;
forming a second etch stop layer over the first dielectric layer;
forming an insulating layer over the second etch stop layer;
removing a first portion of the insulating layer and a portion of the second etch stop layer to expose a portion of the first dielectric layer;
forming a second dielectric layer over the second etch stop layer and the first dielectric layer;
removing a portion of the second dielectric layer, a portion of the first dielectric layer, a second portion of the insulating layer, and a portion of the first etch stop layer to form an opening and expose the conductive line; and
filling the opening with conductive material to form a via and a trench, wherein a junction of the via and the trench is aligned with an interface between the second etch stop layer and the insulating layer.

15. The method of claim 14 , further comprising applying a photoresist over the insulating layer after removing the portion of the insulating layer and the portion of the second etch stop layer to expose the portion of the first dielectric layer.

16. The method of claim 14 , further comprising forming a third etch stop layer over the second dielectric layer and the conductive material.

17. The method of claim 16 , further comprising forming a third dielectric layer over the third etch stop layer.

18. The method of claim 17 , further comprising forming additional conductive material over the third dielectric layer.

19. The method of claim 14 , wherein filling the opening with the conductive material comprises forming both a via and a trench within the opening.

20. The method of claim 14 , wherein the insulating layer is formed of silicon oxide.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Chen Chien-Han
• Chiu Chien-Chih
• Chang Shih-Yu
• Lin Da-Wei
• Chen Y T

Classifications

• H10W20/081

  by forming openings in the dielectric parts · CPC title

• H10W20/056

  by filling conductive material into holes, grooves or trenches · CPC title

• H10W20/43

  Layouts of interconnections · CPC title

• H10W20/42

  Vias, e.g. via plugs · CPC title

• H10W20/075

  of multilayered thin functional dielectric layers · CPC title