Memory device

Patent metadata

Field	Value
Publication number	US-11615840-B2
Application number	US-202017022580-A
Country	US
Kind code	B2
Filing date	Sep 16, 2020
Priority date	Sep 19, 2019
Publication date	Mar 28, 2023
Grant date	Mar 28, 2023

Abstract

According to one embodiment, a memory device includes a memory cell including a resistance change memory element in which a plurality of data values according to resistance are allowed to be set, and a selector element connected to the resistance change memory element in series, a word line supplying a select signal for selecting the resistance change memory element by the selector element to the memory cell, a bit line to which a data signal according to a data value set in the resistance change memory element is read, a load circuit connected to the memory cell in series and functioning as a load, and a comparator circuit which compares a voltage obtained by the load circuit with a plurality of reference voltages.

First claim

What is claimed is:

1. A memory device comprising:
a memory cell including a resistance change memory element in which a plurality of data values according to resistance are allowed to be set, and a selector element connected to the resistance change memory element in series;
a word line which supplies a select signal for selecting the resistance change memory element by the selector element to the memory cell;
a bit line to which a data signal according to a data value set in the resistance change memory element selected by the selector element is read from the memory cell;
a load circuit connected to the memory cell in series and functioning as a load for the resistance change memory element; and
a comparator circuit which compares a voltage obtained by the load circuit with a plurality of reference voltages.

2. The memory device of claim 1 , wherein
the load circuit has a nonlinear current-voltage characteristic.

3. The memory device of claim 1 , wherein
the load circuit has a logarithmic current-voltage characteristic.

4. The memory device of claim 1 , wherein
the load circuit has a linear current-voltage characteristic.

5. The memory device of claim 1 , wherein
the load circuit includes a two-terminal element having a nonlinear current-voltage characteristic.

6. The memory device of claim 5 , wherein
the two-terminal element is a diode.

7. The memory device of claim 1 , wherein
the load circuit includes a diode-connected three-terminal element.

8. The memory device of claim 1 , wherein
the load circuit includes a resistor element.

9. The memory device of claim 1 , wherein
a plurality of resistance states according to a fall speed of an applied voltage are allowed to be set in the resistance change memory element.

10. The memory device of claim 1 , wherein
the resistance change memory element is a phase change memory (PCM) element, an interfacial phase change memory (iPCM) element, a resistive random access memory (ReRAM) element or a conductive bridge random access memory (CBRAM) element.

11. The memory device of claim 1 , wherein
the comparator circuit compares a voltage obtained at a connection point between the memory cell and the load circuit with the plurality of reference voltages.

12. The memory device of claim 1 , wherein
the comparator circuit compares the voltage obtained by the load circuit with the plurality of reference voltages in a transition period before the voltage obtained by the load circuit reaches a constant value.

13. The memory device of claim 1 , wherein
the comparator circuit compares the voltage obtained by the load circuit with the plurality of reference voltages in a saturated stage after the voltage obtained by the load circuit reaches a constant value.

14. The memory device of claim 1 , wherein
the comparator circuit includes a plurality of reference voltage generation circuits which generate the plurality of reference voltages, and
each of the reference voltage generation circuits includes a reference resistor element, a reference selector element connected to one end of the reference resistor element in series, and a reference load circuit connected to the other end of the reference resistor element in series and generating corresponding one of the reference voltages.

15. The memory device of claim 14 , wherein
a circuit including the reference resistor element, the reference selector element and the reference load circuit has a same circuit structure as that of a circuit including the resistance change memory element, the selector element and the load circuit.

16. The memory device of claim 14 , wherein
a resistance distribution characteristic of the resistance change memory element includes a plurality of resistance distribution characteristic portions corresponding to the data values, respectively, and satisfies a following formula:
log R refx-x+1 =(log R x +log R x+1 )/2

where x is a positive integer, and resistance of a center of the x th resistance distribution characteristic portion is R x , and resistance of a center of the x+1 th resistance distribution characteristic portion is R x+1 , and resistance of the reference resistor element having resistance between the resistance R x and the resistance R x+1 is R refx−x+1 .

Assignees

• Kioxia Corp

Inventors

• Ogiwara Ryu
• Takashima Daisaburo
• Iizuka Takahiko

Classifications

• G11C13/004 Primary

  Reading or sensing circuits or methods · CPC title

• G11C13/0069

  Writing or programming circuits or methods · CPC title

• G11C13/0026

  Bit-line or column circuits · CPC title

• G11C13/0004

  comprising amorphous/crystalline phase transition cells · CPC title

• G11C13/0028

  Word-line or row circuits · CPC title