Nonvolatile semiconductor storage apparatus

Patent metadata

Field	Value
Publication number	US-10210930-B2
Application number	US-201615219232-A
Country	US
Kind code	B2
Filing date	Jul 25, 2016
Priority date	Feb 20, 2014
Publication date	Feb 19, 2019
Grant date	Feb 19, 2019

Abstract

A nonvolatile semiconductor storage apparatus is provided. To a data node and a reference node, a first transistor and a second transistor are respectively connected. In a data state determining operation, in the case where voltage is applied to the data node and reference node, the first and second transistors operate as precharge transistors in a first operation mode, and operate as mirror transistors in a second operation mode. The first and second operation modes are switched.

First claim

What is claimed is:

1. A nonvolatile semiconductor storage apparatus comprising:
a memory cell that includes at least a first terminal and a second terminal;
a reference cell that includes at least a third terminal and a fourth terminal;
a readout circuit connected to the first terminal and the third terminal;
a first transistor connected to the first terminal; and
a second transistor connected to the third terminal,
wherein a gate of the first transistor and a gate of the second transistor are connected in common, the nonvolatile semiconductor storage apparatus further comprising a switch for electrically short-circuiting and disconnecting between the gates of the first and second transistors and a drain or a source of the second transistor, and
the switch electrically short-circuits and disconnects between the gates of the first and second transistors and a terminal of the readout circuit connected to the third terminal.

2. The nonvolatile semiconductor storage apparatus according to claim 1 , further comprising a control circuit that has a first control terminal connected to the gate of the first transistor and has a second control terminal connected to the switch, the second control terminal for controlling short-circuiting and disconnecting of the switch, wherein the control circuit controls the first control terminal and the second control terminal.

3. The nonvolatile semiconductor storage apparatus according to claim 2 , further comprising at least a plurality of the memory cells.

4. The nonvolatile semiconductor storage apparatus according to claim 2 , wherein
the first transistor and the second transistor are P-type metal-oxide-semiconductor (PMOS) transistors,
in a first operation mode, the control circuit sets the first control terminal to energize the first and second transistors, sets the second control terminal to disconnect the switch, and causes the first transistor and the second transistor to operate as precharge transistors that respectively apply a first voltage to the first terminal and the third terminal, and
in a second operation mode, the control circuit sets the first control terminal to attain high impedance, sets the second control terminal to short-circuit the switch, and causes the first transistor and the second transistor to operate as mirror transistors that respectively apply the first voltage to the first terminal and the third terminal.

5. The nonvolatile semiconductor storage apparatus according to claim 4 , wherein the first transistor and the second transistor are N-type metal-oxide-semiconductor (NMOS) transistors.

6. The nonvolatile semiconductor storage apparatus according to claim 4 , wherein
the reference cell includes at least two resistors having one ends connected in parallel to the third terminal or the fourth terminal, and
other ends of the resistors are electrically connected to the fourth terminal when the one ends of the resistors are connected to the third terminal, or to the third terminal when the one ends of the resistors are connected to the fourth terminal, according to the first operation mode or the second operation mode.

7. A nonvolatile semiconductor storage apparatus comprising:
a memory cell;
a reference cell; and
a readout circuit that determines a data state based on a voltage difference resulting from a current difference between the memory cell and the reference cell to which voltage is applied,
wherein
a first transistor is connected to the memory cell and a second transistor is connected to the reference cell,
in a first operation mode, the first transistor and the second transistor operate as precharge transistors,
in a second operation mode, the first transistor and the second transistor operate as mirror transistors,
the nonvolatile semiconductor storage apparatus switches between the first operation mode and the second operation mode during operation
the memory cell is a variable resistance nonvolatile memory cell,
in a normal readout operation and in a rewrite operation, a reduced resistance verifying operation and an increased resistance verifying operation are performed, the reduced resistance verifying operation being a readout operation of verifying a resistance value after a resistance reducing operation, the increased resistance verifying operation being a readout operation of verifying a high resistance state after a resistance increasing operation,
in the first operation mode, the normal readout operation is performed, and
in the second operation mode, at least one of the increased resistance verifying operation and the reduced resistance verifying operation is performed.

8. A nonvolatile semiconductor storage apparatus comprising:
a memory cell that includes at least a first terminal and a second terminal,
a reference cell that includes at least a third terminal and a fourth terminal; and
a readout circuit that is connected to a data node and a reference node,
wherein the first terminal and a first transistor are connected to each other, and
the third terminal and a second transistor are connected to each other, the gates of the first transistor and the second transistor are connected in common, the nonvolatile semiconductor storage apparatus further comprising a first circuit that controls, voltage between the first terminal and the second terminal and voltage between the third terminal and the fourth terminal,
the voltage between the first terminal and the second terminal and the voltage between the third terminal and the fourth terminal controlled by the first circuit during a normal readout operation differ from the respective voltages during a verifying operation, the verifying operation being a write completion operation of the nonvolatile memory cell,
the memory cell is a variable resistance nonvolatile memory cell,
each of a reduced resistance verifying operation and an increased resistance verifying operation is performed as a verifying operation, the reduced resistance verifying operation being a readout operation of verifying a resistance value after a resistance reducing operation, the increased resistance verifying operation being a readout operation of verifying a high resistance state after a resistance increasing operation, and
the voltage between the first terminal and the second terminal and the voltage between the third terminal and the fourth terminal controlled by the first circuit differ respectively between the reduced resistance verifying operation and the increased resistance verifying operation.

9. A nonvolatile semiconductor storage apparatus comprising:
a memory cell that includes at least a first terminal and a second terminal;
a reference cell that includes at least a third terminal and a fourth terminal;
a readout circuit that is connected to a data node and a reference node;
a P-type metal-oxide-semiconductor (PMOS) transistor that has a source connected to a first power supply and has a drain connected to the data node;
a PMOS transistor that has a source connected to the first power supply and has a drain connected the reference node;
a first circuit that controls voltage between the first terminal and the second terminal and voltage between the third terminal and the fourth terminal; the first circuit comprising:
a first N-type metal-oxide-semiconductor (NMOS) transistor that has a source connected to the first terminal and has a drain connected to the data node; and
a second NMOS transistor that has a source connected to the third terminal and has a drain connected to the reference node; and
a clamp voltage switching circuit that controls a voltage of a gate of the first NMOS transistor and a voltage of a gate of the second NMOS transistor, wherein
the gate of the fir

Assignees

• Panasonic Ip Man Co Ltd

Inventors

• Nakayama Masayoshi
• Murakuki Yasuo
• Maruyama Takafumi

Classifications

• G11C13/0002

  using resistive RAM [RRAM] elements · CPC title

• G11C13/0064

  Verifying circuits or methods · CPC title

• G11C11/1673

  Reading or sensing circuits or methods · CPC title

• G11C16/28

  using differential sensing or reference cells, e.g. dummy cells · CPC title

• G11C2013/0054

  Read is performed on a reference element, e.g. cell, and the reference sensed value is used to compare the sensed value of the selected cell · CPC title