Dual redundant memory radiation hardening

Patent metadata

Field	Value
Publication number	US-11614995-B2
Application number	US-202117450716-A
Country	US
Kind code	B2
Filing date	Oct 13, 2021
Priority date	Dec 21, 2020
Publication date	Mar 28, 2023
Grant date	Mar 28, 2023

Abstract

A method for storing data includes determining, using a first match line, that a match word satisfies a first content addressable memory (CAM) word stored in a CAM array, wherein the CAM array is configured to store a second CAM word that matches the first CAM word. The method further includes determining that a first parity bit associated with the first CAM word matches a first parity of the first CAM word. The method further includes, in response to determining that the first parity bit associated with the first CAM word matches the first parity determining, using the first match line, a first random access memory (RAM) word stored in a RAM array and outputting the first RAM word.

First claim

What is claimed is:

1. A method for storing data, the method comprising:
determining, using a first match line, that a match word satisfies a first content addressable memory (CAM) word stored in a CAM array, wherein the CAM array is configured to store a second CAM word that matches the first CAM word to provide dual mode redundancy;
in response to determining that the match word satisfies the first CAM word, determining whether a first parity bit associated with the first CAM word matches a first parity of the first CAM word to prevent a false match operation; and
in response to determining that the first parity bit associated with the first CAM word matches the first parity of the first CAM word:
determining, using the first match line, a first random access memory (RAM) word stored in a RAM array, wherein the RAM array is configured to store a second RAM word that matches the first RAM word and wherein a second match line associates the second CAM word and the second RAM word; and
outputting the first RAM word.

2. The method of claim 1 , comprising, before outputting the first RAM word:
determining, using a second match line, that the match word satisfies the second CAM word;
in response to determining that the match word satisfies the second CAM word, determining whether a second parity bit associated with the second CAM word matches a second parity of the second CAM word; and
in response to determining that the second parity bit associated with the second CAM word does not match the second parity of the second CAM word, refraining from outputting the second RAM word.

3. The method of claim 1 , further comprising determining the first parity bit as a majority of three or more parity bits associated with the first CAM word.

4. The method of claim 1 , further comprising fetching the first parity bit from the RAM array.

5. The method of claim 1 , comprising:
receiving CAM data indicating a plurality of bit values and RAM data indicating a second plurality of bit values;
setting the first CAM word and the second CAM word to match the CAM data; and
setting the first RAM word and the second RAM word to match the RAM data.

6. The method of claim 5 , comprising setting the first parity bit associated with the first CAM word and the second parity bit associated with the second CAM word to a parity of the CAM data.

7. The method of claim 1 , wherein the CAM array comprises one or more NOR CAM cells.

8. The method of claim 1 , wherein the CAM array comprises one or more NAND CAM cells.

9. The method of claim 1 , wherein the CAM array comprises one or more SRAM CAM cells.

10. A device for storing data, the device comprising:
a content addressable memory (CAM) array;
a random access memory (RAM) array; and
circuitry configured to:
determine, using a first match line, that a match word satisfies a first CAM word stored in the CAM array, wherein the CAM array is configured to store a second CAM word that matches the first CAM word to provide dual mode redundancy;
in response to determining that the match word satisfies the first CAM word, determining whether a first parity bit associated with the first CAM word matches a first parity of the first CAM word to prevent a false match operation; and
in response to determining that the first parity bit associated with the first CAM word matches the first parity of the first CAM word:
determine, using the first match line, a first RAM word stored in the RAM array, wherein the RAM array is configured to store a second RAM word that matches the first RAM word and wherein a second match line associates the second CAM word and the second RAM word; and
output the first RAM word.

11. The device of claim 10 , wherein the circuitry is configured to, before outputting the first RAM word:
determine, using a second match line, that the match word satisfies the second CAM word;
in response to determining that the match word satisfies the second CAM word, determining whether a second parity bit associated with the second CAM word matches a second parity of the second CAM word; and
in response to determining that the second parity bit associated with the second CAM word does not match the second parity of the second CAM word, refraining from outputting the second RAM word.

12. The device of claim 10 , wherein the circuitry is further configured to determine the first parity bit as a majority of three or more parity bits associated with the first CAM word.

13. The device of claim 10 , wherein the circuitry is further configured to fetch the first parity bit from the RAM array.

14. The device of claim 10 , wherein the circuitry is further configured to:
receive CAM data indicating a plurality of bit values and RAM data indicating a second plurality of bit values;
set the first CAM word and the second CAM word to match the CAM data; and
set the first RAM word and the second RAM word to match the RAM data.

15. The device of claim 14 , wherein the circuitry is further configured to set the first parity bit associated with the first CAM word and the second parity bit associated with the second CAM word to a parity of the CAM data.

16. The device of claim 10 , wherein the CAM array comprises one or more NOR CAM cells.

17. The device of claim 10 , wherein the CAM array comprises one or more NAND CAM cells.

18. The device of claim 10 , wherein the CAM array comprises one or more SRAM CAM cells.

19. A device for storing data, the device comprising circuitry configured to:
determine, using a first match line, that a match word satisfies a first content addressable memory (CAM) word stored in a CAM array, wherein the CAM array is configured to store a second CAM word that matches the first CAM word to provide dual mode redundancy;
in response to determining that the match word satisfies the first CAM word, determining whether a first parity bit associated with the first CAM word matches a first parity of the first CAM word to prevent a false match operation; and
in response to determining that the first parity bit associated with the first CAM word matches the first parity of the first CAM word:
determine, using the first match line, a first random access memory (RAM) word stored in a RAM array, wherein the RAM array is configured to store a second RAM word that matches the first RAM word and wherein a second match line associates the second CAM word and the second RAM word; and
output the first RAM word.

20. The device of claim 19 , wherein the circuitry is configured to, before outputting the first RAM word:
determine, using a second match line, that the match word satisfies the second CAM word;
in response to determining that the match word satisfies the second CAM word, determining whether a second parity bit associated with the second CAM word matches a second parity of the second CAM word; and
in response to determining that the second parity bit associated with the second CAM word does not match the second parity of the second CAM word, refraining from outputting the second RAM word.

Assignees

• Honeywell Int Inc

Inventors

• Nelson David K
• Rabe Robert
• Goike Keith

Classifications

• G11C29/52

  Protection of memory contents; Detection of errors in memory contents · CPC title

• G11C15/04 Primary

  using semiconductor elements · CPC title

• G06F11/1004 Primary

  to protect a block of data words, e.g. CRC or checksum (G06F11/1076 takes precedence; security arrangements for protecting computers or computer systems against unauthorized activity G06F21/00) · CPC title

• G06F11/1064

  in cache or content addressable memories · CPC title

• G11C2029/0411

  Online error correction · CPC title