Apparatus and method to identify the source of an interrupt

Patent metadata

Field	Value
Publication number	US-11614939-B2
Application number	US-202117359337-A
Country	US
Kind code	B2
Filing date	Jun 25, 2021
Priority date	Mar 28, 2020
Publication date	Mar 28, 2023
Grant date	Mar 28, 2023

Abstract

An apparatus and method for processing non-maskable interrupt source information. For example, one embodiment of a processor comprises: a plurality of cores comprising execution circuitry to execute instructions and process data; local interrupt circuitry comprising a plurality of registers to store interrupt-related data including non-maskable interrupt (NMI) data related to a first NMI; and non-maskable interrupt (NMI) processing mode selection circuitry, responsive to a request, to select between at least two NMI processing modes to process the first NMI including: a first NMI processing mode in which the plurality of registers are to store first data related to a first NMI, wherein no NMI source information related to a source of the NMI is included in the first data, and a second NMI processing mode in which the plurality of registers are to store both the first data related to the first NMI and second data comprising NMI source information indicating the NMI source.

First claim

What is claimed is:

1. A system comprising:
a system memory to store instructions and data;
a memory interconnect coupled to the system memory; and
a processor comprising a plurality of dies integrated on a processor package, a first die of the plurality of dies comprising:
a plurality of cores comprising execution circuitry to execute the instructions and process the data;
local interrupt circuitry comprising a plurality of registers to store interrupt-related data including non-maskable interrupt (NMI) data related to a first NMI; and
non-maskable interrupt (NMI) processing mode selection circuitry, responsive to a request, to select between at least two NMI processing modes to process the first NMI including:
a first NMI processing mode in which the plurality of registers are to store first data related to a first NMI, wherein no NMI source information related to a source of the NMI is included in the first data, and
a second NMI processing mode in which the plurality of registers are to store both the first data related to the first NMI and second data comprising NMI source information indicating the NMI source.

2. The system of claim 1 wherein the first data is to be stored in a first set of fields in the plurality of registers and the second data is to be stored in a second field in at least one of the plurality of registers.

3. The system of claim 2 wherein the second field comprises an interrupt vector field which is not utilized in the first NMI processing mode.

4. The system of claim 3 wherein the interrupt vector field comprises an 8-bit field.

5. The system of claim 3 wherein the first data comprises a delivery mode indication to indicate the first NMI is a non-maskable interrupt.

6. The system of claim 1 wherein the plurality of registers include a local vector table (LVT) and an interrupt command register (ICR).

7. The system of claim 3 wherein the request is generated by an operating system (OS) or virtual machine monitor (VMM), the OS or VMM to receive an error code specifying the NMI source information and to responsively store the second data in the plurality of registers.

8. The system of claim 1 further comprising:
an input-output memory management unit (IOMMU) couped to the memory interconnect, the IOMMU comprising an interrupt remapping table (IRT) to store a portion of the first data when in the first NMI processing mode and to additionally store a portion of the second data when in the second NMI processing mode.

9. The system of claim 1 further comprising:
a communication device to couple the processor to a network.

10. The system of claim 1 further comprising:
a storage device coupled to the processor.

11. The system of claim 1 wherein the first die of the plurality of dies further comprises:
graphics processing logic to perform graphics operations.

12. A method comprising:
executing instructions and processing data on a plurality of cores of a semiconductor die of a processor package, the processor package coupled to a system memory, the system memory to store the instructions and the data;
storing interrupt-related data including non-maskable interrupt (NMI) data related to a first NMI on local interrupt circuitry comprising a plurality of registers;
selecting between at least first and second NMI processing modes to process the first NMI;
storing first data in the plurality of registers related to a first NMI when in the first NMI processing mode, wherein no NMI source information related to a source of the NMI is included in the first data; and
storing second data in addition to the first data in the plurality of registers related to the first NMI, the second data comprising NMI source information indicating the NMI source.

13. The method of claim 12 wherein the first data is to be stored in a first set of fields in the plurality of registers and the second data is to be stored in a second field in at least one of the plurality of registers.

14. The method of claim 13 wherein the second field comprises an interrupt vector field which is not utilized in the first NMI processing mode.

15. The method of claim 14 wherein the interrupt vector field comprises an 8-bit field.

16. The method of claim 14 wherein the first data comprises a delivery mode indication to indicate the first NMI is a non-maskable interrupt.

17. The method of claim 12 wherein the plurality of registers include a local vector table (LVT) and an interrupt command register (ICR).

18. The method of claim 14 wherein the request is generated by an operating system (OS) or virtual machine monitor (VMM), the OS or VMM to receive an error code specifying the NMI source information and to responsively store the second data in the plurality of registers.

19. The method of claim 12 further comprising:
storing a portion of the first data in an interrupt remapping table (IRT) of an input-output memory management unit (IOMMU) when in the first NMI processing mode; and
additionally storing a portion of the second data in the IRT when in the second NMI processing mode.

20. The method of claim 1 further comprising:
communicating over a network.

21. The system of claim 1 further comprising:
storing the data in a storage device.

22. The system of claim 1 further comprising:
performing graphics operations responsive to one or more of the instructions.

Assignees

• Intel Corp

Inventors

• Raj Ashok
• Kleen Andreas
• Neiger Gilbert
• Strong Beeman
• Brandt Jason
• Vakharwala Rupin
• Huxel Jeff
• Novakovsky Larisa
• Ouziel Ido
• Jayakumar Sarathy

Classifications

• G06F9/4812 Primary

  by interrupt, e.g. masked · CPC title

• G06F2209/481

  Exception handling · CPC title

• G06F9/30098 Primary

  Register arrangements · CPC title

• G06F15/80

  comprising an array of processing units with common control, e.g. single instruction multiple data processors (G06F15/82 takes precedence {; for correlation function computation G06F17/15}) · CPC title

• G06F9/5005

  to service a request · CPC title