Orthogonal differential vector signaling

Patent metadata

Field	Value
Publication number	US-11611377-B2
Application number	US-202117235184-A
Country	US
Kind code	B2
Filing date	Apr 20, 2021
Priority date	Apr 30, 2010
Publication date	Mar 21, 2023
Grant date	Mar 21, 2023

Abstract

Using a transformation based at least in part on a non-simple orthogonal or unitary matrix, data may be transmitted over a data bus in a manner that is resilient to one or more types of signal noise, that does not require a common reference at the transmission and acquisition points, and/or that has a pin-efficiency that is greater than 50% and may approach that of single-ended signaling. Such transformations may be implemented in hardware in an efficient manner. Hybrid transformers that apply such transformations to selected subsets of signals to be transmitted may be used to adapt to various signal set sizes and/or transmission environment properties including noise and physical space requirements of given transmission environments.

First claim

What is claimed is:

1. A method comprising:
obtaining an input vector comprising a plurality of multilevel signals, each multilevel signal having a signal value selected from a set of more than two signal values;
generating, using a balancer, a set of analog multilevel signals and a reference voltage from the input vector;
generating, using an encoder, a set of output signals from the set of analog multilevel signals, each output signal generated on a respective wire of a multi-wire bus responsive to a respective additive computation of the set of analog multilevel signals with respect to the reference voltage using a respective sequence of analog adders and subtractors, each respective sequence of analog adders and subtractors determined according to a respective row of a set of mutually orthogonal rows of an orthogonal matrix; and
transmitting the set of output signals over the multi-wire bus.

2. The method of claim 1 , wherein each multilevel signal of the plurality of multilevel signals is represented as a multi-bit value.

3. The method of claim 1 , wherein the plurality of multilevel signals comprises N−1 signals, and wherein the set of output signals comprises N output signals, wherein N is an integer power of two greater than 2.

4. The method of claim 1 , wherein the orthogonal matrix is a Hadamard matrix.

5. The method of claim 4 , wherein one of the reference voltage is a constant value.

6. The method of claim 5 , wherein the reference voltage is a non-zero value ‘V’.

7. The method of claim 5 , wherein the constant value is zero.

8. The method of claim 1 , wherein each respective additive computation is performed by a series of additions and subtractions as determined by ‘+1’ and ‘−1’ entries, respectively, in the respective row of the orthogonal matrix.

9. The method of claim 1 , further comprising forming a second set of signals using a decoder, each respective signal of the second set based on a transformation of the set of signals with a respective row of the set of mutually orthogonal rows of the orthogonal matrix, wherein each respective signal in the second set of signals has an analog value selected from a respective set of more than two values; and
reproducing original information from the second set of signals.

10. The method of claim 9 , wherein reproducing original information from the second set of signals comprises generating a multi-bit value for each signal of the second set of signals.

11. An apparatus comprising:
a storage medium configured to provide an input vector to a balancer, the input vector comprising a plurality of multilevel signals, each multilevel signal having a signal value selected from a set of more than two signal values;
a balancer configured to generate a set of analog multilevel signals and a reference voltage;
an encoder configured to generate a set of output signals from the input vector of multilevel signals, each output signal generated on a respective wire of a multi-wire bus responsive to a respective additive computation of the set of analog multilevel signals with respect to the reference voltage using a respective sequence of analog adders and subtractors, each respective sequence of analog adders and subtractors determined according to a respective row of a set of mutually orthogonal rows of an orthogonal matrix, the set of mutually orthogonal rows further orthogonal to a common mode row of all ones; and
a set of signal path drivers configured to transmit the set of output signals over the multi-wire bus.

12. The apparatus of claim 11 , wherein the storage medium is configured to store each multilevel signal of the plurality of multilevel signals as a multi-bit value.

13. The apparatus of claim 11 , wherein the plurality of multilevel signals comprises N−1 signals, and wherein the set of output signals comprises N output signals, wherein N is an integer power of two greater than 2.

14. The apparatus of claim 11 , wherein the orthogonal matrix is a Hadamard matrix.

15. The apparatus of claim 14 , the reference voltage is a constant value.

16. The apparatus of claim 15 , wherein the constant value is a non-zero value ‘V’.

17. The apparatus of claim 15 , wherein the constant value is zero.

18. The apparatus of claim 11 , wherein the encoder is configured to generate each respective additive computation by forming a series of additions and subtractions as determined by ‘+1’ and ‘−1’ entries, respectively, in the respective row of the orthogonal matrix.

19. The apparatus of claim 11 , further comprising a decoder configured to receive the set of output signals, and to responsively form a second set of signals, each respective signal of the second set based on a transformation of the set of output signals with a respective row of the set of mutually orthogonal rows of the orthogonal matrix, wherein each respective signal in the second set of signals has an analog value selected from a respective set of more than two values; and
a detector configured to reproduce original information from the second set of signals.

20. The apparatus of claim 19 , wherein the detector is configured to generate a multi-bit value for each signal of the second set of signals to reproduce original information.

Assignees

• Ecole Polytechnique Fed Lausanne Epfl

Inventors

• Cronie Harm
• Shokrollahi Amin

Classifications

• H04L25/0272 Primary

  Arrangements for coupling to multiple lines, e.g. for differential transmission · CPC title

• H04L5/0007

  the frequencies being orthogonal, e.g. OFDM(A) or DMT · CPC title

• H04B7/0413 Primary

  MIMO systems · CPC title

• H04L25/4906

  using binary codes · CPC title

• H04B10/54

  Intensity modulation · CPC title