Cap layer on a polarization layer to preserve channel sheet resistance

Patent metadata

Field	Value
Publication number	US-11610971-B2
Application number	US-201816222976-A
Country	US
Kind code	B2
Filing date	Dec 17, 2018
Priority date	Dec 17, 2018
Publication date	Mar 21, 2023
Grant date	Mar 21, 2023

Abstract

An integrated circuit structure comprises a base layer that includes a channel region, wherein the base layer and the channel region include group III-V semiconductor material. A polarization layer stack is over the base layer, wherein the polarization layer stack comprises a buffer stack, an interlayer over the buffer stack, a polarization layer over the interlayer. A cap layer stack is over the polarization layer to reduce transistor access resistance.

First claim

What is claimed is:

1. An integrated circuit structure, comprising:
a base layer that includes a channel region, wherein the base layer and the channel region include group III-V semiconductor material;
a polarization layer stack over the base layer; and
a cap layer stack over the polarization layer stack, wherein the cap layer stack comprises a nitride compound of silicon, gallium, aluminum, or boron, and does not fill pits and defects of a top surface of the polarization layer stack.

2. The integrated circuit structure of claim 1 , wherein the cap layer stack comprises at least one of SiNx, GaN, AIN, and BN.

3. The integrated circuit structure of claim 1 , wherein the cap layer stack comprises a first cap layer made of a III-N material, and a second cap layer comprising a dielectric.

4. The integrated circuit structure of claim 3 , wherein the first cap layer is doped with a Si dopant.

5. The integrated circuit structure of claim 1 , wherein the cap layer stack has a thickness range of approximately 1-20 nm.

6. The integrated circuit structure of claim 1 , wherein the polarization layer stack comprises a buffer stack, an interlayer over the buffer stack, and a polarization layer over the interlayer.

7. The integrated circuit structure of claim 6 , wherein the buffer stack of the polarization layer stack comprises gallium and nitrogen, and the interlayer and the polarization layer of the polarization layer stack comprise aluminum and nitrogen.

8. The integrated circuit structure of claim 1 , wherein the base layer and the channel region comprise gallium and nitrogen.

9. The integrated circuit structure of claim 1 , wherein the cap layer stack reduces channel sheet resistance.

10. A transistor, comprising:
a base layer that includes a channel region, wherein the base layer and the channel region comprise gallium and nitride;
a polarization layer stack over the base layer;
a gate electrode over the polarization layer stack; and
source and drain regions adjacent to the channel region,
wherein the polarization layer stack comprises a buffer stack, an interlayer over the buffer stack, a polarization layer over the interlayer, and a cap layer stack over the polarization layer, wherein the cap layer stack comprises a nitride compound of silicon, gallium, aluminum, or boron, and does not fill pits and defects of a top surface of the polarization layer stack.

11. The transistor of claim 10 , wherein the cap layer stack comprises at least one of SiNx, GaN, AIN, and BN.

12. The transistor of claim 10 , wherein the cap layer stack comprises a first cap layer made of a III-N material, and a second cap layer comprises a dielectric.

13. The transistor of claim 12 , wherein the first cap layer is doped with a Si dopant.

14. The transistor of claim 10 , wherein the cap layer stack has a thickness range of approximately 1-20 nm.

15. The transistor of claim 10 , wherein the buffer stack of the polarization layer stack comprises gallium and nitrogen.

16. The transistor of claim 10 , wherein the interlayer and the polarization layer of the polarization layer stack comprise aluminum and nitrogen.

17. The transistor of claim 10 , wherein the cap layer stack reduces channel sheet resistance.

18. An integrated circuit structure, comprising:
a base layer that includes a channel region, wherein the base layer and the channel region include group III-V semiconductor material;
a polarization layer stack over the base layer; and
a cap layer stack is conformal with the polarization layer stack, wherein wherein the cap layer stack comprises a nitride compound of silicon, gallium, aluminum, or boron, and fills pits and defects of a top surface of the polarization layer stack.

19. A transistor, comprising:
a base layer that includes a channel region, wherein the base layer and the channel region comprise gallium and nitride;
a polarization layer stack over the base layer;
a gate electrode over the polarization layer stack; and
source and drain regions adjacent to the channel region,
wherein the polarization layer stack comprises a buffer stack, an interlayer over the buffer stack, a polarization layer over the interlayer, and a cap layer stack over the polarization layer, wherein the cap layer stack comprises a nitride compound of silicon, gallium, aluminum, or boron, and fills pits and defects of a top surface of the polarization layer stack.

Assignees

• Intel Corp

Inventors

• Dasgupta Sansaptak
• Radosavljevic Marko
• Then Han Wui
• Nidhi Nidhi
• Ramaswamy Rahul
• Rode Johann
• Fischer Paul
• Hafez Walid

Classifications

• H10P14/69433

  the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz · CPC title

• H10P14/3416

  Nitrides · CPC title

• H10P14/3216

  Nitrides · CPC title

• H10W10/17

  formed using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title

• H10W10/014

  using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title