Pixel array substrate

Patent metadata

Field	Value
Publication number	US-11610920-B2
Application number	US-202017017706-A
Country	US
Kind code	B2
Filing date	Sep 11, 2020
Priority date	Dec 4, 2019
Publication date	Mar 21, 2023
Grant date	Mar 21, 2023

Abstract

A pixel array substrate includes data lines, first gate lines, pixel structures, first common lines, and conductive line sets. The conductive line sets are arranged in a first direction. Each of the conductive line sets includes first conductive line groups and a second conductive line group sequentially arranged in the first direction. Each of the first conductive line groups includes second gate lines and a second common line. The second conductive line group includes first auxiliary lines and a second common line. An arrangement order of the second gate lines and the second common line of each of the first conductive line groups in the first direction are the same as an arrangement order of the first auxiliary lines and the second common line of the second conductive line group in the first direction, respectively.

First claim

What is claimed is:

1. A pixel array substrate, comprising:
a base;
a plurality of data lines disposed on the base and arranged in a first direction;
a plurality of first gate lines disposed on the base and arranged in a second direction staggered with the first direction;
a plurality of pixel structures disposed on the base and electrically connected to the data lines and the first gate lines;
a plurality of first common lines disposed on the base, arranged in the second direction, and overlapped with the pixel structures; and
a plurality of conductive line sets disposed on the base and arranged in the first direction, wherein each of the conductive line sets comprises:
a plurality of first conductive line groups, wherein each of the first conductive line groups comprises a plurality of second gate lines and a second common line, the second gate lines of each of the first conductive line groups are electrically connected to a plurality of first gate lines of the first gate lines, and the second common line of each of the first conductive line groups is electrically connected to at least one of the first common lines; and
a second conductive line group, wherein the first conductive line groups and the second conductive line group are sequentially arranged in the first direction, the second conductive line group comprises a second gate line, a first auxiliary line, and a second common line, the second gate line of the second conductive line group is electrically connected to one of the first gate lines, and the second common line of the second conductive line group is electrically connected to at least one of the first common lines;

wherein an arrangement order of the second gate lines and the second common line of each of the first conductive line groups in the first direction is the same as an arrangement order of the second gate line, the first auxiliary line, and the second common line of the second conductive line group in the first direction, respectively.

2. The pixel array substrate of claim 1 , wherein a signal of the first auxiliary line of the second conductive line group and a gate-off signal of one of the second gate lines of one of the first conductive line groups are substantially the same.

3. The pixel array substrate of claim 1 , wherein the first auxiliary line of the second conductive line group has a DC potential DC 1 , the second common line of one of the first conductive line groups has a DC potential DC 2 , and |DC 1 −DC 1 |>1 V.

4. The pixel array substrate of claim 1 , wherein the pixel structures are arranged in a plurality of pixel columns, the pixel columns are arranged in the first direction, the plurality of pixel structures of each of the pixel columns are arranged in the second direction, and each of the first conductive line groups comprises:
a plurality of second auxiliary lines, wherein each of the second auxiliary lines and one of the second gate lines of the first conductive line group are disposed between two adjacent pixel columns, and each of the second auxiliary lines is structurally separated from the second gate line of the first conductive line group.

5. The pixel array substrate of claim 4 , wherein the second auxiliary lines of the first conductive line group are electrically connected to the first auxiliary line of the second conductive line group.

6. The pixel array substrate of claim 1 , wherein the second gate lines and the second common line of each of the first conductive line groups are sequentially arranged in the first direction, and the first auxiliary line, the second gate line, and the second common line of the second conductive line group are sequentially arranged in the first direction.

Assignees

• Au Optronics Corp

Inventors

• Chen Ping-Wen
• Lee Min-Tse
• Cheng Sheng-Yen
• Chung Yueh-Hung
• Wu Yueh-Chi
• Liao shu-wen
• Yu Ti-Kuei
• Hsu Ya-Ling
• Liao Chen-Hsien

Classifications

• H10D86/441

  Interconnections, e.g. scanning lines · CPC title

• H10D86/60 Primary

  wherein the TFTs are in active matrices · CPC title

• G09G2300/0426

  Layout of electrodes and connections · CPC title

• G09F9/30 Primary

  in which the desired character or characters are formed by combining individual elements (panels comprising a number of electrodes in a single cell controlling light arriving from an independent light source, e.g. electro-optical or magneto-optical cell, G02F1/00) · CPC title

• G09G3/00 Primary

  Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes · CPC title