Liquid crystal display device

Patent metadata

Field	Value
Publication number	US-9646559-B2
Application number	US-201313960099-A
Country	US
Kind code	B2
Filing date	Aug 6, 2013
Priority date	Aug 10, 2012
Publication date	May 9, 2017
Grant date	May 9, 2017

Abstract

A display device including a panel having a display area and first, second, third and fourth non-display areas formed at an outer portion of the display area, said first non-display area facing the second non-display area, and the third non-display area facing the fourth non-display area; a data driver disposed in the first non-display area, and configured to drive a plurality of data lines provided in a first direction in the display area; a gate driver disposed in the second non-display area and configured to drive a plurality of gate lines provided in a second direction vertical to the first direction in the display area; a timing controller configured to drive the data driver and the gate driver; and a plurality of link lines in the display area and extending from the gate driver and provided in parallel to the data lines respectively connected to the gate lines.

First claim

What is claimed is:

1. A display device, comprising:
a panel including a display area and first, second, third and fourth non-display areas formed at an outer portion of the display area, said first non-display area facing the second non-display area, and the third non-display area facing the fourth non-display area;
a data driver disposed in the first non-display area, and configured to drive a plurality of data lines provided in a first direction in the display area;
a gate driver disposed in the second non-display area facing the first non-display area with the data driver disposed therein and configured to drive a plurality of gate lines provided in a second direction vertical to the first direction in the display area;
a timing controller configured to drive the data driver and the gate driver; and
a plurality of link lines in the display area and extending from the gate driver and provided in parallel to the data lines respectively connected to the gate lines,
wherein at least two link lines are connected to one gate line and connect to the gate driver,
wherein the at least two link lines connected to the one gate line are separated from each other by a distance interval greater than or equal to ⅓ of a length of the one gate line, and
wherein the at least two link lines are perpendicular to the one gate line.

2. The display device of claim 1 , wherein a P number of pixels arranged on one horizontal line in the display area are driven in a double rate driving (DRD) type by using two gate lines and P/2 number of data lines.

3. The display device of claim 1 , wherein a common voltage area for applying a common voltage to the display area is formed in at least one of the third and fourth non-display areas.

4. The display device of claim 1 , wherein the at least two link lines simultaneously apply a same scan signal at a same timing to the one gate line, and
wherein at least two other link lines among the plurality of link lines are disposed between the at least two link lines connected to the one gate line.

5. The display device of claim 1 , wherein the at least two link lines connected to the one gate line apply separate scan signals, output from the gate driver, to the one gate line.

6. The display device of claim 1 , wherein the gate driver has “x” number of gate drivers,
wherein a number of the link lines equals “x” times the number of gate lines, and
wherein “x” is an integer.

7. The display device of claim 1 , wherein the gate driver is disposed in a GIP type in the non-display area, or is connected to the non-display areas in a tape carrier package (TCP) type or a chip-on film (COF) type.

8. The display device of claim 1 , wherein a plurality of scan signals are applied to the gate lines through the link lines in overlap with each other.

9. The display device of claim 8 , wherein a rising edge of a second scan signal applied to a second gate line occurs before a falling edge of a first scan signal applied to a first gate line signal so the scan signals overlap with each other.

10. The display device of claim 8 , further comprising:
a plurality of first switching parts in at least one of the third non-display area and the fourth non-display area, and respectively connected to corresponding gate lines; and
a first signal line connected to each of the first switching parts,
wherein a clock signal applied from the timing controller to the gate driver is also applied to the plurality of first switching parts via the first signal line to turn on respective switching parts and apply an additional voltage to the corresponding gate line.

11. The LCD device of claim 10 , further comprising:
a plurality of second switching parts formed in the first non-display region, each second switching part being connected to a corresponding data line in a one-to-one manner; and
a second signal line connected to each of the second switching parts and configured to receive a data voltage from the data driver so as to turn on a corresponding second switching part.

12. A method of driving a display device including a panel having a display area and first, second, third and fourth non-display areas formed at an outer portion of the display area, said first non-display area facing the second non-display area, and the third non-display area facing the fourth non-display area, and including a data driver disposed in the first non-display area, a plurality of data lines provided in a first direction in the display area, a gate driver disposed in the second non-display area facing the first non-display area with the data driver disposed therein, a plurality of gate lines provided in a second direction vertical to the first direction in the display area, a timing controller, and a plurality of link lines in the display area and extending from the gate driver and provided in parallel to the data lines respectively connected to the gate lines, the method comprising
applying a plurality of scan signals, via the gate driver, to the gate lines through the link lines such that a rising edge of a second scan signal applied to a second gate line occurs before a falling edge of a first scan signal applied to a first gate line signal so the scan signals overlap with each other,
wherein at least two link lines are connected to one gate line and connect to the gate driver,
wherein the at least two link lines connected to the one gate line are separated from each other by a distance interval greater than or equal to ⅓ of a length of the one gate line, and
wherein the at least two link lines are perpendicular to the one gate line.

13. The method of claim 12 , wherein a P number of pixels arranged on one horizontal line in the display area are driven in a double rate driving (DRD) type by using two gate lines and P/2 number of data lines.

14. The method of claim 12 , wherein a common voltage area for applying a common voltage to the display area is formed in at least one of the third and fourth non-display areas.

15. The method of claim 12 , wherein the at least two link lines simultaneously apply a same scan signal at a same timing to the one gate line, and
wherein at least two other link lines among the plurality of link lines are disposed between the at least two link lines connected to the one gate line.

16. The method of claim 12 , wherein the at least two link lines connected to the one gate line apply separate scan signals, output from the gate driver, to the one gate line.

17. The method of claim 12 , wherein the gate driver has “x” number of gate drivers,
wherein a number of the link lines equals “x” times the number of gate lines, and
wherein “x” is an integer.

18. The method of claim 12 , wherein the gate driver is disposed in a GIP type in the non-display area, or is connected to the non-display areas in a tape carrier package (TCP) type or a chip-on film (COF) type.

Assignees

• Lg Display Co Ltd

Inventors

• Min Woong Ki
• Baek Heum Seok
• Son Mi Young
• Kim Ho June
• Park Yoon San
• Park Sung Gon

Classifications

• G09G3/3677 Primary

  suitable for active matrices only · CPC title

• G09G2310/0218

  with collection of electrodes in groups for n-dimensional addressing · CPC title

• G09G2310/0281

  Arrangement of scan or data electrode driver circuits at the periphery of a panel not inherent to a split matrix structure · CPC title

• G09G2300/0426

  Layout of electrodes and connections · CPC title

• G09G2320/0223

  Compensation for problems related to R-C delay and attenuation in electrodes of matrix panels, e.g. in gate electrodes or on-substrate video signal electrodes · CPC title