Package-on-package (POP) type semiconductor packages

Patent metadata

Field	Value
Publication number	US-11610871-B2
Application number	US-202016874722-A
Country	US
Kind code	B2
Filing date	May 15, 2020
Priority date	Sep 10, 2019
Publication date	Mar 21, 2023
Grant date	Mar 21, 2023

Abstract

Provided are package-on-package (POP)-type semiconductor packages including a lower package having a first size and including a lower package substrate in which a lower semiconductor chip is, an upper redistribution structure on the lower package substrate and the lower semiconductor chip, and alignment marks. The packages may also include an upper package having a second size smaller than the first size and including an upper package substrate and an upper semiconductor chip. The upper package substrate may be mounted on the upper redistribution structure of the lower package and electrically connected to the lower package, and the upper semiconductor chip may be on the upper package substrate. The alignment marks may be used for identifying the upper package, and the alignment marks may be below and near outer boundaries of the upper package on the lower package.

First claim

What is claimed is:

1. A package-on-package (POP)-type semiconductor package comprising:
a lower package having a first size and comprising a lower package substrate, an upper redistribution structure, and alignment marks, wherein the lower package substrate comprises a lower semiconductor chip therein, and the upper redistribution structure is on the lower package substrate and the lower semiconductor chip;
an upper package having a second size smaller than the first size and comprising an upper package substrate and an upper semiconductor chip, wherein the upper package substrate is mounted on the upper redistribution structure of the lower package and is electrically connected to the lower package, and the upper semiconductor chip is on the upper package substrate; and
a cover layer extending on the upper redistribution structure,
wherein the alignment marks indicate an outline of the upper package and are below and adjacent to the outline of the upper package, and
the alignment marks are on the upper redistribution structure and are at a level equal to the cover layer.

2. The POP-type semiconductor package of claim 1 , wherein each of the alignment marks comprises a solid pattern identifiable by a vision camera.

3. The POP-type semiconductor package of claim 1 , wherein the alignment marks comprise two alignment marks that are below and adjacent to two opposing corner portions of the upper package, respectively.

4. The POP-type semiconductor package of claim 1 , wherein each of the alignment marks comprises a first portion overlapped by the upper package and a second portion not overlapped by the upper package, and
the second portions of the alignment marks have an identical shape.

5. A package-on-package (POP)-type semiconductor package comprising:
a lower package having a first size and comprising a lower package substrate, an upper redistribution structure, a lower semiconductor chip, and alignment marks, wherein the lower semiconductor chip is in the lower package substrate, and the upper redistribution structure extends on the lower package substrate and the lower semiconductor chip; and
an upper package having a second size smaller than the first size and comprising an upper package substrate and an upper semiconductor chip, wherein the upper package substrate is mounted on the upper redistribution structure of the lower package and is electrically connected to the lower package, and the upper semiconductor chip is on the upper package substrate,
wherein each of the alignment marks comprises a first portion overlapped by the upper package, and
wherein each of the alignment marks further comprises a second portion not overlapped by the upper package.

6. The POP-type semiconductor package of claim 5 , wherein the alignment marks are between the lower package substrate and the upper package substrate.

7. The POP-type semiconductor package of claim 5 , wherein the upper redistribution structure comprises an upper redistribution layer and an upper redistribution insulating layer, and
the upper redistribution insulating layer is a transparent organic layer.

8. The POP-type semiconductor package of claim 5 , wherein the lower package substrate comprises a cavity extending through the lower package substrate, and
the lower semiconductor chip is in the cavity of the lower package substrate, and
the POP-type semiconductor package further comprises a lower molding layer that is on the lower semiconductor chip and the lower package and in the cavity of the lower package substrate between the lower semiconductor chip and the lower package substrate.

9. The POP-type semiconductor package of claim 5 , wherein the upper redistribution structure comprises an upper redistribution insulating layer and an upper redistribution layer, and
the alignment marks are in the upper redistribution insulating layer and comprise a material the same as a material of the upper redistribution layer.

10. The POP-type semiconductor package of claim 5 , wherein the upper redistribution structure comprises an upper redistribution insulating layer and an upper redistribution layer, and
the alignment marks are in the upper redistribution structure and are at a level equal to the upper redistribution layer.

11. A package-on-package (POP)-type semiconductor package comprising:
a lower package having a first size and comprising a lower package substrate, an upper redistribution structure, a lower semiconductor chip, and alignment marks, wherein the lower semiconductor chip is in the lower package substrate, and the upper redistribution structure extends on the lower package substrate and the lower semiconductor chip; and
an upper package having a second size smaller than the first size and comprising an upper package substrate and an upper semiconductor chip, wherein the upper package substrate is mounted on the upper redistribution structure of the lower package and is electrically connected to the lower package, and the upper semiconductor chip is on the upper package substrate,
wherein the alignment marks indicate an outline of the upper package, and the alignment marks are below and adjacent to the outline of the upper package,
the alignment marks are between the lower package substrate and the upper package substrate, and
each of the alignment marks comprises a first portion overlapped by the upper package and a second portion not overlapped by the upper package.

12. The POP-type semiconductor package of claim 11 , wherein the lower package substrate comprises a cavity extending through a body of the lower package substrate, and the lower semiconductor chip is in the cavity of the body of the lower package substrate.

13. The POP-type semiconductor package of claim 11 , wherein the upper package has a quadrangular shape, and
each of the alignment marks is below and adjacent to a respective one of two opposing corner portions of the upper package.

14. The POP-type semiconductor package of claim 11 , wherein each of the alignment marks is a solid pattern identifiable by a vision camera.

15. The POP-type semiconductor package of claim 11 , wherein the lower semiconductor chip comprises a first lower semiconductor chip and a second lower semiconductor chip, and the first and second lower semiconductor chips are in the lower package substrate and spaced apart from each other.

16. The POP-type semiconductor package of claim 11 , wherein the upper redistribution structure comprises an upper redistribution layer and an upper redistribution insulating layer, and
the upper redistribution insulating layer is a transparent organic layer.

17. The POP-type semiconductor package of claim 16 , wherein the alignment marks are in the upper redistribution insulating layer and at a level equal to the upper redistribution layer, and the alignment marks comprise a material the same as a material of the upper redistribution layer.

18. The POP-type semiconductor package of claim 11 , wherein the second portions of the alignment marks have an identical shape.

19. The POP-type semiconductor package of claim 18 , wherein the first portions of the alignment marks have an identical shape.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Lee Minho
• Yoo Jaewook

Classifications

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W90/722

  between stacked chips · CPC title

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W74/15

  on active surfaces of flip-chip devices, e.g. underfills · CPC title

• H10W46/607

  Located on parts of packages, e.g. on encapsulations or on package substrates · CPC title