Air gap between tungsten metal lines for interconnects with reduced rc delay

Patent metadata

Field	Value
Publication number	US-2016013133-A1
Application number	US-201414330950-A
Country	US
Kind code	A1
Filing date	Jul 14, 2014
Priority date	Jul 14, 2014
Publication date	Jan 14, 2016
Grant date	—

Abstract

Systems and methods are directed to a semiconductor device, which includes an integrated circuit, wherein the integrated circuit includes at least a first layer comprising two or more Tungsten lines and at least one air gap between at least two Tungsten lines, the air gaps to reduce capacitance. An interposer is coupled to the integrated circuit, to reduce stress on the two or more Tungsten lines and the at least one air gap. A laminated package substrate may be attached to the interposer such that the interposer is configured to absorb mechanical stress induced by mismatch in coefficient of thermal expansion (CTE) between the laminated package substrate and the interposer and protect the air gap from the mechanical stress.

First claim

What is claimed is:

1 . A semiconductor device comprising:
an integrated circuit comprising a first layer comprising two or more Tungsten lines and at least one air gap between at least two Tungsten lines; and an interposer coupled to the integrated circuit, the interposer configured to reduce stress on the two or more Tungsten lines and the at least one air gap.

2 . The semiconductor device of claim 1 , wherein the Tungsten lines are formed from a Fluorine (F) free process.

3 . The semiconductor device of claim 1 , wherein the Tungsten lines are deposited by physical vapor deposition (PVD).

4 . The semiconductor device of claim 1 , further comprising a second layer comprising one or more Tungsten lines, wherein the second layer is separated from the first layer by a cap layer, and wherein the Tungsten lines of the first layer are connected to Tungsten lines of the second layer through vias.

5 . The semiconductor device of claim 1 , wherein the first layer further comprises an interlayer dielectric material.

6 . The semiconductor device of claim 1 , wherein the Tungsten lines are formed using dual damascene (DD) or etch, followed by chemical mechanical polishing (CMP).

7 . The semiconductor device of claim 1 , wherein the air gap is of narrow width.

8 . The semiconductor device of claim 1 , wherein the interposer is coupled to the integrated circuit using Cu—Cu bonding or hybrid bonding comprising Cu—Cu bonding and oxide-oxide bonding.

9 . The semiconductor device of claim 1 , wherein the interposer further comprises a dielectric layer and one or more metal lines.

10 . The semiconductor device of claim 1 further comprising a laminated package substrate attached to the interposer such that the interposer is configured to absorb mechanical stress induced by mismatch in coefficient of thermal expansion (CTE) between the laminated package substrate and the interposer and protect the air gap from the mechanical stress.

11 . The semiconductor device of claim 1 integrated in at least one semiconductor die.

12 . The semiconductor device of claim 1 , integrated in a device selected from the group consisting of a set top box, music player, video player, entertainment unit, navigation device, communications device, personal digital assistant (PDA), fixed location data unit, and a computer.

13 . A method of forming a semiconductor device, the method comprising:
forming two or more Tungsten lines in a first layer of an integrated circuit; forming at least one air gap between at least two of the Tungsten lines; and coupling an interposer to the integrated circuit to reduce stress on the Tungsten lines and the air gap.

14 . The method of claim 13 , comprising forming the Tungsten lines from a Fluorine (F) free process.

15 . The method of claim 13 , comprising forming the Tungsten lines by physical vapor deposition (PVD).

16 . The method of claim 13 , comprising forming the Tungsten lines using dual damascene (DD) or etch and chemical mechanical polishing (CMP).

17 . The method of claim 13 , comprising coupling the interposer to the integrated circuit by Cu—Cu bonding or hybrid bonding comprising Cu—Cu bonding and oxide-oxide bonding.

18 . The method of claim 13 further comprising attaching a laminated package substrate attached to the interposer such that the interposer is configured to absorb mechanical stress induced by mismatch in coefficient of thermal expansion (CTE) between the laminated package substrate and the interposer and protect the air gap from the mechanical stress.

19 . A semiconductor device comprising:
two or more Tungsten lines in a first layer of an integrated circuit; means for forming at least one air gap between at least two of the Tungsten lines; and coupling means coupled to the integrated circuit, the coupling means to reduce stress on the Tungsten lines and the air gap.

20 . The semiconductor device of claim 19 , further comprising:
a second layer comprising one or more Tungsten lines: a cap means for separating the second layer from the first layer; and and connecting means for connecting the Tungsten lines of the first layer to the Tungsten lines of the second layer.

21 . The semiconductor device of claim 19 further comprising a laminated package substrate attached to the coupling means such that the coupling means is configured to absorb mechanical stress induced by mismatch in coefficient of thermal expansion (CTE) between the laminated package substrate and the coupling means and protect the air gap from the mechanical stress.

Assignees

• Qualcomm Inc

Inventors

• Gu Shiqun
• Nowak Matthew Michael
• Xu Jeffrey Junhao

Classifications

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/701

  characterised by the relative positions of pads or connectors relative to package parts · CPC title

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W70/698

  Semiconductor materials that are electrically insulating, e.g. undoped silicon · CPC title

• H10W20/20

  Interconnections within wafers or substrates, e.g. through-silicon vias [TSV] · CPC title