Laser-releasable bonding materials for 3-D IC applications

Patent metadata

Field	Value
Publication number	US-11610801-B2
Application number	US-202016747271-A
Country	US
Kind code	B2
Filing date	Jan 20, 2020
Priority date	Jan 22, 2019
Publication date	Mar 21, 2023
Grant date	Mar 21, 2023

Abstract

Novel polyketanil-based compositions for use as a laser-releasable composition for temporary bonding and laser debonding processes are provided. The inventive compositions can be debonded using various UV lasers, at wavelengths from about 300 nm to about 360 nm, leaving behind little to no debris. The layers formed from these compositions possess good thermal stabilities and are resistant to common solvents used in semiconductor processing. The compositions can also be used as build-up layers for redistribution layer formation.

First claim

We claim:

1. A temporary bonding method comprising:
providing a stack comprising:
a first substrate having a back surface and a front surface;
a bonding layer adjacent said front surface;
a second substrate having a first surface; and
a release layer between said first surface and said bonding layer, said release layer comprising a polyketanil; and

exposing said release layer to laser energy so as to facilitate separation of said first and second substrates.

2. The method of claim 1 , wherein said polyketanil is crosslinked.

3. The method of claim 1 , wherein said polyketanil is a polymer of a monomer comprising an amine functional group, a ketone functional group, and an aromatic moiety, wherein said amine functional group and said ketone functional group are bonded to said aromatic moiety.

4. The method of claim 3 , wherein said recurring monomer is 4-aminoacetophenone.

5. The method of claim 1 , further comprising one or both of the following:
said front surface is a device surface that comprises an array of devices selected from the group consisting of integrated circuits; MEMS; microsensors; power semiconductors; light-emitting diodes; photonic circuits; interposers; embedded passive devices; and microdevices fabricated on or from silicon, silicon-germanium, gallium arsenide, gallium nitride, and combinations of the foregoing; or
said first surface is a device surface that comprises an array of devices selected from the group consisting of integrated circuits; MEMS; microsensors; power semiconductors; light-emitting diodes; photonic circuits; interposers; embedded passive devices; and microdevices fabricated on or from silicon, silicon-germanium, gallium arsenide, gallium nitride, and combinations of the foregoing.

6. The method of claim 1 , wherein one or both of said first substrate or said second substrate comprises glass or other transparent material.

7. The method of claim 1 , further comprising one or both of the following:
said front surface is a device surface comprising at least one structure selected from the group consisting of: solder bumps; metal posts; metal pillars; and structures formed from a material selected from the group consisting of silicon, polysilicon, silicon dioxide, silicon (oxy)nitride, metal, low k dielectrics, polymer dielectrics, metal nitrides, metal silicides, and combinations of the foregoing; or
said first surface is a device surface comprising at least one structure selected from the group consisting of: solder bumps; metal posts; metal pillars; and structures formed from a material selected from the group consisting of silicon, polysilicon, silicon dioxide, silicon (oxy)nitride, metal, low k dielectrics, polymer dielectrics, metal nitrides, metal silicides, and combinations of the foregoing.

8. The method of claim 1 , further comprising subjecting said stack to processing selected from the group consisting of back-grinding, chemical-mechanical polishing, etching, metallizing, dielectric deposition, patterning, passivation, annealing, and combinations thereof, prior to separating said first and second substrates, prior to separating said first and second substrates.

9. The method of claim 1 , wherein said providing comprises bonding said first and second substrate together to form said stack.

Assignees

• Brewer Science Inc

Inventors

• Prenger Luke
• Southard Arthur O
• Wu Qi
• Liu Xiao

Classifications

• H10W74/142

  the encapsulations exposing the passive side of the semiconductor body · CPC title

• H10W72/07207

  Temporary substrates, e.g. removable substrates · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W74/019

  using temporary auxiliary substrates (H10W74/017 takes precedence) · CPC title

• H10W74/114

  by a substrate and the encapsulations · CPC title