Stacked solid electrolytic capacitor, integrated circuit product and electronic product

US11610741B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-11610741-B2
Application numberUS-202117453339-A
CountryUS
Kind codeB2
Filing dateNov 2, 2021
Priority dateNov 3, 2020
Publication dateMar 21, 2023
Grant dateMar 21, 2023

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A stacked solid electrolytic capacitor is provided in the present disclosure. The stacked solid electrolytic capacitor includes a capacitive module, a conductive module and a packaging structure. The capacitive module includes capacitive units stacked up sequentially. The conductive module includes a positive terminal, a negative terminal and at least one anti-oxidizing layer. The positive terminal is electrically connected to one of the capacitive units. The negative terminal is electrically connected to the one of the capacitive units through a conductive paste layer. The at least one anti-oxidizing layer is arranged between the negative terminal and the conductive paste layer. The packaging structure surrounds the capacitive module and the conductive module. Therefore, it is difficult for an oxide layer forming between the negative terminal and the capacitive units, and the equivalent series resistance of the stacked solid electrolytic capacitor can be reduced.

First claim

Opening claim text (preview).

What is claimed is: 1. A stacked solid electrolytic capacitor, comprising: a capacitive module, wherein the capacitive module comprises a plurality of capacitive units stacked up sequentially, and each of the plurality of capacitive units comprises: a positive portion, wherein the positive portions of the plurality of capacitive units are electrically connected to each other, and the positive portions are bent toward a side of the capacitive module; and a negative portion, wherein the negative portions of the plurality of capacitive units are electrically connected to each other; a conductive module, comprising: a positive terminal, electrically connected to the positive portion of one of the plurality of capacitive units from the side of the capacitive module; a negative terminal, electrically connected to the negative portion of the one of the plurality of capacitive units through a conductive paste layer; and at least one anti-oxidizing layer, arranged between the negative terminal and the conductive paste layer; and a packaging structure, surrounding the capacitive module and the conductive module, wherein the positive terminal and the negative terminal are partially uncovered by the packaging structure; wherein the at least one anti-oxidizing layer comprises a first anti-oxidizing layer and a second anti-oxidizing layer, the first anti-oxidizing layer and the second anti-oxidizing layer are stacked up sequentially along a direction from the negative terminal toward the conductive paste layer, the first anti-oxidizing layer is made of palladium, and the second anti-oxidizing layer is made of gold; and wherein a thickness of the first anti-oxidizing layer is 40 nm-100 nm, and a thickness of the second anti-oxidizing layer is 100 nm. 2. The stacked solid electrolytic capacitor of claim 1 , wherein the positive terminal and the negative terminal are made of copper or copper-zinc alloy. 3. The stacked solid electrolytic capacitor of claim 1 , wherein the conductive module further comprises a nickel layer, and the nickel layer is arranged between the negative terminal and the first anti-oxidizing layer. 4. The stacked solid electrolytic capacitor of claim 3 , wherein a thickness of the nickel layer is 0.1 μm-5 μm. 5. The stacked solid electrolytic capacitor of claim 1 , wherein an interfacial resistance between the negative terminal and the conductive paste layer is less than 1 mΩ. 6. An integrated circuit product, comprising the stacked solid electrolytic capacitor of claim 1 . 7. An electronic product, comprising the stacked solid electrolytic capacitor of claim 1 .

Assignees

Inventors

Classifications

  • H01G4/224Primary

    Housing; Encapsulation · CPC title

  • H01G9/012Primary

    specially adapted for solid capacitors · CPC title

  • Structural combinations {or circuits} for modifying, or compensating for, electric characteristics of electrolytic capacitors · CPC title

  • H01G9/26Primary

    Structural combinations of electrolytic capacitors, rectifiers, detectors, switching devices, light-sensitive or temperature-sensitive devices with each other · CPC title

  • Multiple capacitors, i.e. structural combinations of fixed capacitors · CPC title

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What does patent US11610741B2 cover?
A stacked solid electrolytic capacitor is provided in the present disclosure. The stacked solid electrolytic capacitor includes a capacitive module, a conductive module and a packaging structure. The capacitive module includes capacitive units stacked up sequentially. The conductive module includes a positive terminal, a negative terminal and at least one anti-oxidizing layer. The positive term…
Who is the assignee on this patent?
Apaq Technology Co Ltd
What technology area does this patent fall under?
Primary CPC classification H01G4/224. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Mar 21 2023 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).