Storage system with multiple components and method for use therewith

US11610642B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-11610642-B2
Application numberUS-202117529663-A
CountryUS
Kind codeB2
Filing dateNov 18, 2021
Priority dateAug 26, 2016
Publication dateMar 21, 2023
Grant dateMar 21, 2023

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A storage system with several integrated components and method for use therewith are provided. In one embodiment, a storage system comprising: a plurality of non-volatile memory devices; a controller in communication with the plurality of non-volatile memory devices; a plurality of data buffers in communication with the controller and configured to store data sent between the controller and an input/output bus; and a command and address buffer configured to store commands and addresses sent from a host, wherein the command and address buffer is further configured to synchronize data flow into and out of the plurality of data buffer; wherein at least three of the above components are integrated with each other.

First claim

Opening claim text (preview).

What is claimed is: 1. A method for a storage system comprising non-volatile memory, a data buffer, a driver and a controller, the method comprising: receiving, by the driver from a host, a write command, an address and a write identifier; providing, by the driver to the controller, the write command, the address and the write identifier; obtaining, by the data buffer from the host, data; transferring, from the data buffer to the controller, data requested by the write identifier; accepting, by a first buffer of the controller, the requested data; moving, to a second buffer of the controller, the requested data; and writing, to the non-volatile memory, the requested data, wherein the requested data is protected from power-fail before the requested data is written to the non-volatile memory. 2. The method of claim 1 , comprising: issuing a write indicator based on the accepting of the requested data by the first buffer of the controller; and issuing a write persist indicator based on the moving of the requested data to the second buffer of the controller. 3. The method of claim 2 , wherein: issuing the write indicator and issuing the write persist indicator cause incrementing a write counter and a write persist counter, respectively; and receiving the write command by the driver from the host, is initiated based on a value of the write counter and a value of the write persist counter. 4. The method of claim 1 , wherein the requested data is protected from the power-fail when the requested data is moved to the second buffer of the controller. 5. The method of claim 1 , wherein the data buffer obtains the data from the host after a predetermined time delay after receiving, by the driver from the host, the write command and the address. 6. The method of claim 1 , comprising: obtaining, by the driver from the host, a read command, a second address and a read identifier; transferring, by the driver to the controller, the read command, the second address and the read identifier; and providing, to a second data buffer, the read command and the read identifier but not the second address. 7. The method of claim 6 , comprising: obtaining, by the controller, second requested data from the non-volatile memory; transferring, to the second data buffer by the controller, the second requested data; and placing, by the second data buffer, the second requested data into an allocated space identified by the read identifier. 8. A data storage system, comprising: non-volatile memory; a data buffer; a driver; and a controller comprising a first buffer and a second buffer, wherein: the driver is configured to receive, from a host, a write command, an address and a write identifier; the driver is configured to provide, to the controller, the write command, the address and the write identifier; the data buffer is configured to obtain, from the host, data; the data buffer is configured to transfer, to the controller, data requested by the write identifier; the first buffer of the controller is configured to accept the requested data; the controller is configured to move, to the second buffer of the controller, the requested data; and the controller is configured to write, to the non-volatile memory, the requested data, wherein the requested data is protected from power-fail before the requested data is written to the non-volatile memory. 9. The data storage system of claim 8 , wherein the controller is configured to cause: issuing a write indicator based on accepting the requested data by the first buffer of the controller; and issuing a write persist indicator based on moving the requested data to the second buffer of the controller. 10. The data storage system of claim 9 , wherein issuing the write indicator and issuing the write persist indicator cause incrementing a write counter and a write persist counter, respectively. 11. The data storage system of claim 10 , wherein receipt of the write command by the driver from the host is initiated based on a value of the write counter and a value of the write persist counter. 12. The data storage system of claim 8 , wherein the requested data is protected from the power-fail when the requested data is moved to the second buffer of the controller. 13. The data storage system of claim 8 , wherein the data buffer is configured to obtain the data from the host after a predetermined time delay after the driver receives the write command from the host. 14. The data storage system of claim 8 , comprising a second data buffer, wherein: the driver is configured to obtain, from the host, a read command, a second address and a read identifier; the driver is configured to provide, to the controller, the read command, the second address and the read identifier; and the driver is configured to provide, to the second data buffer, the read command and the read identifier but not the second address. 15. The data storage system of claim 14 , wherein: the controller is configured to obtain second requested data from the non-volatile memory; the controller is configured to transfer, to the second data buffer, the second requested data; and the second data buffer is configured to place the second requested data into an allocated space identified by the read identifier. 16. The data storage system of claim 8 , wherein: the data buffer comprise first input and output buffers, an input buffer, an output buffer, second input and output buffers, and a synchronization logic; an output of the first input and output buffers is connected to the synchronization logic; the synchronization logic is connected to an input of the input buffer; an output of the input buffer is connected to an input of the second input and output buffers; an output of the second input and output buffers is connected to an input of the output buffer; an output of the output buffer is connected to the synchronization logic; and the synchronization logic is connected to an input of the first input and output buffers. 17. The data storage system of claim 8 , wherein: the data buffer is configured to receive a first clock signal and a second clock signal; a rate the first clock signal is higher than a rate of the second clock signal; the rate of the first clock signal is comparable to a rate of a clock signal generated by the host; and the rate of the second clock signal is comparable to a rate of a clock signal used by the controller. 18. The data storage system of claim 17 , wherein the data buffer is configured to receive, from the driver, a command bus signal. 19. An apparatus, comprising: non-volatile memory; a controller; means for receiving, from a host, a write command, an address and a write identifier; means for providing, by the means for receiving to the controller, the write command, the address and the write identifier; means for obtaining data from the host; means for transferring, from the means for obtaining to the controller, data requested by the write identifier; means for accepting, by a first buffer of the controller, the requested data; means for moving, to a second buffer of the controller, the requested data; and means for writing, to the non-volatile memory, the requested data, wherein the requested data is protected from power-fail before the requested data is written to the non-volatile memory. 20. The apparatus of claim 19 , wherein: the requested data is protected from the power-fail when the requested data is moved to the second bu

Assignees

Inventors

Classifications

  • in relation to life time, e.g. increasing Mean Time Between Failures [MTBF] · CPC title

  • using arrangements adapted for a specific error detection or correction feature · CPC title

  • Supports for storage elements {, e.g. memory modules}; Mounting or fixing of storage elements on such supports · CPC title

  • G11C29/52Primary

    Protection of memory contents; Detection of errors in memory contents · CPC title

  • Non-volatile semiconductor memory arrays · CPC title

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What does patent US11610642B2 cover?
A storage system with several integrated components and method for use therewith are provided. In one embodiment, a storage system comprising: a plurality of non-volatile memory devices; a controller in communication with the plurality of non-volatile memory devices; a plurality of data buffers in communication with the controller and configured to store data sent between the controller and an …
Who is the assignee on this patent?
Sandisk Technologies Llc
What technology area does this patent fall under?
Primary CPC classification G11C29/52. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Mar 21 2023 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 12 related publications on this page (citations in our corpus or others sharing the same primary CPC).