Memory controller architecture with improved memory scheduling efficiency

Patent metadata

Field	Value
Publication number	US-9811263-B1
Application number	US-201414319103-A
Country	US
Kind code	B1
Filing date	Jun 30, 2014
Priority date	Jun 30, 2014
Publication date	Nov 7, 2017
Grant date	Nov 7, 2017

Abstract

Integrated circuits that include memory interface and controller circuitry for communicating with external memory are provided. The memory interface and controller circuitry may include a user logic interface, a memory controller, and a physical layer input-output interface. The user logic interface may be operated in a first clock domain. The memory controller may be operated in a second clock domain. The physical layer interface may be operated in a third clock domain that is an integer multiple of the second clock domain. The user logic interface may include only user-dependent blocks. The physical layer interface may include memory protocol agnostic blocks and/or memory protocol specific blocks. The memory controller may include both memory protocol agnostic blocks and memory protocol dependent blocks. The memory controller may include one or more color pipelines for scheduling memory requests in a parallel arbitration scheme.

First claim

What is claimed is:

1. A method for operating memory controller circuitry that communicates with external memory, the method comprising:
receiving a memory access request at the memory controller circuitry, wherein the memory controller circuitry includes a plurality of color pipelines that are operated in parallel to process memory access requests for different portions of the external memory;
decoding the memory access request to identify a target portion of the external memory that is to be accessed; and
determining whether the target portion of the external memory has already been assigned to one of the plurality of color pipelines.

2. The method defined in claim 1 , further comprising:
in response to determining that the target portion of the external memory has already been assigned to one of the plurality of color pipelines, assigning the memory access request to that particular color pipeline.

3. The method defined in claim 2 , further comprising:
in response to determining that the target portion of the external memory has not yet been assigned to one of the plurality of color pipelines, assigning the memory access request to an empty color pipeline.

4. The method defined in claim 3 , further comprising:
forwarding the memory access request to a selected one of a read command queue and a write command buffer in the assigned color pipeline.

5. The method defined in claim 4 , further comprising:
when the memory access request has been dispatched to the external memory, determining whether the target portion of the external memory is currently being accessed.

6. The method defined in claim 5 , further comprising:
in response to determining that the target portion of the external memory is no longer being accessed, determining whether the target portion of the external memory is being targeted by any entries in the read command queue and the write command buffer in that color pipeline.

7. The method defined in claim 6 , further comprising:
in response to determining that the target portion of the external memory is not being targeted by any entries in the read command queue and the write command buffer in that color pipeline and by a newly arriving memory access request, making that color pipeline available to receive new memory access requests that target other portions in the external memory.

8. The method defined in claim 1 , wherein determining whether the target portion of the external memory has already been assigned to one of the plurality of color pipelines by referring to a color assignment lookup table.

9. The method defined in claim 1 , further comprising:
in response to determining that the target portion of the external memory has not yet been assigned to one of the plurality of color pipelines, assigned the memory access request to an empty color pipeline.

10. A method for operating memory controller circuitry that communicates with external memory, the method comprising:
receiving a memory command at the memory controller circuitry, wherein the memory controller circuitry includes a plurality of color pipelines that are operated in parallel to process memory commands; and
determining a selected color pipeline in the plurality of color pipelines to which the received memory command for even distribution of incoming memory commands targeting different portions of the external memory among the plurality of color pipelines.

11. The method defined in claim 10 , further comprising:
assigning the memory command a first color that is associated with a first color pipeline in the plurality of color pipelines.

12. The method defined in claim 11 , further comprising:
receiving an additional memory command that targets the same portion in the external memory as the memory command that has been assigned the first color; and
assigning the additional memory command the first color.

13. The method defined in claim 11 , further comprising:
receiving an additional memory command that targets a different portion in the external memory as the memory command that has been assigned the first color; and
assigning the additional memory command a second color that is associated with a second color pipeline in the plurality of color pipelines that is different than the first color pipeline.

14. The method defined in claim 11 , wherein the memory command targets a first portion in the external memory, the method further comprising:
when all memory commands in the first color pipeline have been dispatched to the external memory, allowing the first color pipeline to process a memory command that targets a second portion in the external memory that is different than the first portion.

15. The method defined in claim 14 , further comprising:
after all the memory commands in the first color pipeline have been dispatched to the external memory, receiving a new memory command that targets the second portion in the external memory; and
assigning the new memory command the first color.

16. Memory controller circuitry that communicates with external memory, comprising:
an input that receives memory access requests; and
a plurality of color pipelines that are operated in parallel to process the memory access requests accessing different portions of the external memory, wherein each color pipeline in the plurality of color pipeline includes a read command queue and a write command buffer.

17. The memory controller circuitry defined in claim 16 , wherein the read command queue comprises a collapsible shift register.

18. The memory controller circuitry defined in claim 17 , wherein the read command queue comprises:
a plurality of storage elements that latches data for a corresponding entry in the read command queue; and
at least one multiplexing circuit coupled to each data storage element in the plurality of storage elements.

19. The memory controller circuitry defined in claim 18 , wherein the read command queue further comprises:
an additional multiplexing circuit coupled to at least one data storage element in the plurality of storage elements; and
a logic gate that controls the additional multiplexing circuit.

20. The memory controller circuitry defined in claim 16 , wherein the read command queue prioritizes older memory access requests above newer memory access requests.

Assignees

• Altera Corp

Inventors

• Teh Chee Hak

Classifications

• G06F2212/1024

  Latency reduction · CPC title

• G06F3/0659

  Command handling arrangements, e.g. command buffers, queues, command scheduling · CPC title

• G06F3/0679

  Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP] · CPC title

• G06F13/1668

  Details of memory controller · CPC title

• G06F3/0656

  Data buffering arrangements · CPC title