Shift register unit and driving method thereof, gate drive circuit and display device

Patent metadata

Field	Value
Publication number	US-11610524-B2
Application number	US-201816470534-A
Country	US
Kind code	B2
Filing date	Nov 19, 2018
Priority date	May 16, 2018
Publication date	Mar 21, 2023
Grant date	Mar 21, 2023

Abstract

A shift register unit and a driving method thereof, a gate drive circuit and a display device. The shift register unit includes a first input circuit, an output circuit and a first output pull-down circuit. The first input circuit is configured to charge a pull-up node in response to a first clock signal and reset the pull-up node in response to the first clock signal; the output circuit is configured to output a second clock signal to an output terminal under a control of a level of the pull-up node; the first output pull-down circuit is configured to denoise the output in response to a third clock signal.

First claim

What is claimed is:

1. A gate drive circuit comprising the shift register unit, wherein the gate drive circuit comprises a first clock signal line, a second clock signal line, a third clock signal line and a fourth clock signal line, wherein
the shift register unit comprises a first input circuit, an output circuit and a first output denoising circuit,
wherein the first input circuit is configured to charge a first node in response to a first clock signal and reset the first node in response to the first clock signal,
the output circuit is configured to output a second clock signal to an output terminal under a control of a level of the first node, and
the first output denoising circuit is configured to denoise the output terminal in response to a third clock signal,
the first input circuit is connected to a first input terminal,
a signal output from the first input terminal and a signal output from the output terminal partially overlap with each other, and overlapping time between the signal output from the first input terminal and the signal output from the output terminal is half of a high-level pulse width of the first clock signal,
the shift register unit further comprises a second input circuit, a first clock signal terminal, a second clock signal terminal, a third clock signal terminal, and a fourth clock signal terminal, wherein the first clock signal terminal, the second clock signal terminal, the third clock signal terminal, and the fourth clock signal terminal are configured for inputting the first clock signal, the second clock signal, the third clock signal, and a fourth clock signal into the first input circuit, the output circuit, the first output denoising circuit, and the second input circuit, respectively,
the first clock signal terminal of the shift register unit of a (4n-3)th stage is connected with the first clock signal line, the second clock signal terminal of the shift register unit of the (4n-3)th stage is connected with the second clock signal line, the third clock signal terminal of the shift register unit of the (4n-3)th stage is connected with the third clock signal line, and the fourth clock signal terminal of the shift register unit of the (4n-3)th stage is connected with the fourth clock signal line,
the first clock signal terminal of the stage shift register unit of a (4n-2)th stage is connected with the second clock signal line, the second clock signal terminal of the (4n-2)th stage shift register unit is connected with the fourth clock signal line, the third clock signal terminal of the (4n-2)th stage shift register unit is connected with the first clock signal line, and the fourth clock signal terminal of the shift register unit of the (4n-2)th stage is connected with the third clock signal line,
the first clock signal terminal of the stage shift register unit of a (4n-1)th stage is connected with the fourth clock signal line, the second clock signal terminal of the (4n-1)th stage shift register unit is connected with the third clock signal line, the third clock signal terminal of the shift register unit of the (4n-1)th stage is connected with the second clock signal line, and the fourth clock signal terminal of the shift register unit of the (4n-1)th stage is connected with the first clock signal line,
the first clock signal terminal of the shift register unit of a (4n)th stage is connected with the third clock signal line, the second clock signal terminal of the 4n-th stage shift register unit is connected with the first clock signal line, the third clock signal terminal of the 4n-th stage shift register unit is connected with the fourth clock signal line, and the fourth clock signal terminal of the shift register unit of the (4n)th stage is connected with the second clock signal line, and n is an integer greater than 0.

2. A display device comprising the gate drive circuit according to claim 1 .

3. The gate drive circuit according to claim 1 , wherein the second input circuit is configured to denoise the first node in response to a fourth clock signal.

4. The gate drive circuit according to claim 3 , wherein the second input circuit comprises a fourth transistor,
a gate of the fourth transistor is configured to be connected to the fourth clock signal terminal to receive the fourth clock signal, a first electrode of the fourth transistor is configured to be connected to the first node, and a second electrode of the fourth transistor is configured to be connected to a second input terminal to receive a second input signal.

5. The gate drive circuit according to claim 1 , wherein the shift register unit further comprises a first node control circuit and a second output denoising circuit,
wherein the first node control circuit is configured to control a level of a second node under a control of the level of the first node, and
the second output denoising circuit is configured to denoise the output terminal under a control of the level of the second node.

6. The gate drive circuit according to claim 5 , further comprising a second node control circuit,
wherein the second node control circuit is configured to control the level of the second node in response to the second clock signal.

7. The gate drive circuit according to claim 6 , wherein the second output denoising circuit comprises a sixth transistor,
a gate of the sixth transistor is configured to be connected to the second node, a first electrode of the sixth transistor is configured to be connected to the output terminal, and a second electrode of the sixth transistor is configured to be connected to a first voltage terminal to receive a first voltage.

8. The gate drive circuit according to claim 5 , wherein the first node control circuit comprises a fifth transistor;
a gate of the fifth transistor is configured to be connected to the first node, a first electrode of the fifth transistor is configured to be connected to the second node, and a second electrode of the fifth transistor is configured to be connected to a first voltage terminal to receive a first voltage.

9. The gate drive circuit according to claim 1 , wherein the first input circuit comprises a first transistor,
a gate of the first transistor is configured to be connected to the first clock signal terminal to receive the first clock signal, a first electrode of the first transistor is configured to be connected to the first input terminal to receive a first input signal, and a second electrode of the first transistor is configured to be connected to the first node.

10. The gate drive circuit according to claim 9 , wherein the second node control circuit comprises a second capacitor,
a first electrode of the second capacitor is configured to be connected to the second node, and a second electrode of the second capacitor is configured to be connected to the second clock signal terminal to receive the second clock signal.

11. The gate drive circuit according to claim 1 , wherein the output circuit comprises a second transistor and a first capacitor,
a gate of the second transistor is configured to be connected to the first node, a first electrode of the second transistor is configured to be connected to the second clock signal terminal to receive the second clock signal, and a second electrode of the second transistor is configured to be connected to the output terminal, and
a first electrode of the first capacitor is configured to be connected to the gate of the second transistor, and a second electrode of the first capacitor is configured to be connected to the second electrode of the second transistor.

12. The gate drive circuit according to claim 1 , wherein the first output denoising circuit comprises a

Assignees

• Chengdu Boe Optoelect Tech Co
• Boe Technology Group Co Ltd

Inventors

• Luo Hao
• Hu Like

Classifications

• G09G2310/0283

  Arrangement of drivers for different directions of scanning · CPC title

• G09G3/3677

  suitable for active matrices only · CPC title

• G11C19/28

  using semiconductor elements (G11C19/14, G11C19/36 take precedence) · CPC title

• G09G3/3674 Primary

  Details of drivers for scan electrodes · CPC title

• G09G2310/0267

  Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays · CPC title