Apparatus and method for processing floating-point numbers

Patent metadata

Field	Value
Publication number	US-11609741-B2
Application number	US-202016932923-A
Country	US
Kind code	B2
Filing date	Jul 20, 2020
Priority date	Jul 19, 2019
Publication date	Mar 21, 2023
Grant date	Mar 21, 2023

Abstract

Circuits and associated methods for processing two floating-point numbers (A, B) to generate a sum (A+B) of the two numbers and a difference (A-B) of the two numbers include calculating (806) a sum (|A|+|B|) of the absolute values of the two floating-point numbers, using a same-sign floating-point adder (1020), to produce a first result. The method further comprises calculating (808) a difference (|A|−|B|) of the absolute values to produce a second result. The sum (A+B) and the difference (A-B) are generated (810, 812) based on the first result (|A|+|B|), the second result (|A|−|B|), and the sign of each floating-point number.

First claim

What is claimed is:

1. A circuit configured to process an input set comprising two floating-point numbers (A, B), each of the floating-point numbers (A, B) having a sign, to generate a sum (A+B) and a difference (A-B) of the two floating-point numbers (A, B), the circuit comprising:
an input, configured to receive the two floating-point numbers (A, B) of the input set;
a same-sign floating-point adder, configured to calculate a sum of absolute values of the two floating-point numbers (A, B), to produce a first result;
a floating-point subtractor, configured to calculate a difference of the absolute values of the two floating-point numbers (A, B), to produce a second result; and
multiplexing and sign-correction logic, configured to generate the sum (A+B) of the two floating-point numbers (A, B) and the difference (A-B) of the two floating-point numbers (A, B) based on: the first result, the second result, and the sign of each of the floating-point numbers (A, B),
wherein the same-sign floating-point adder is implemented in fixed function circuitry configured to add together floating-point numbers having the same sign, and wherein the same-sign floating-point adder does not include circuitry configured to add together numbers having different signs.

2. The circuit of claim 1 , wherein the floating-point subtractor is implemented in fixed function circuitry.

3. The circuit of claim 1 , wherein the floating-point subtractor is implemented by a mixed-sign floating-point adder.

4. The circuit of claim 2 , wherein the floating-point subtractor is implemented by a mixed-sign floating-point adder.

5. The circuit of claim 1 , wherein the multiplexing and sign-correction logic is configured to:
generate the sum (A+B) of the two floating-point numbers (A, B) from one of the first result and the second result; and
generate the difference (A-B) of the two floating-point numbers (A, B) from the other of the first result and the second result.

6. The circuit of claim 1 , wherein the multiplexing and sign-correction logic is configured to correct a sign of the first result and a sign of the second result based on the sign of each of the two floating-point numbers (A, B).

7. The circuit of claim 5 , wherein the multiplexing and sign-correction logic is configured to correct a sign of the first result and a sign of the second result based on the sign of each of the two floating-point numbers (A, B).

8. A non-transitory computer readable storage medium having stored thereon a computer readable description of a circuit, which, when processed in an integrated circuit manufacturing system, causes the integrated circuit manufacturing system to manufacture an integrated circuit embodying the circuit,
wherein the circuit is configured to process an input set comprising two floating-point numbers (A, B), each of the floating-point numbers (A, B) having a sign, to generate a sum (A+B) and a difference (A-B) of the two floating-point numbers (A, B), the circuit comprising:
an input, configured to receive the two floating-point numbers (A, B) of the input set;
a same-sign floating-point adder, configured to calculate a sum of absolute values of the two floating-point numbers (A, B), to produce a first result;
a floating-point subtractor, configured to calculate a difference of the absolute values of the two floating-point numbers (A, B), to produce a second result; and
multiplexing and sign-correction logic, configured to generate the sum (A+B) of the two floating-point numbers (A, B) and the difference (A-B) of the two floating-point numbers (A, B) based on: the first result, the second result, and the sign of each of the floating-point numbers (A, B),
wherein the same-sign floating-point adder is implemented in fixed function circuitry configured to add together floating-point numbers having the same sign, and wherein the same-sign floating-point adder does not include circuitry configured to add together numbers having different signs.

9. The non-transitory computer readable storage medium of claim 8 , wherein the floating-point subtractor is implemented in fixed function circuitry.

10. The non-transitory computer readable storage medium of claim 8 , wherein the floating-point subtractor is implemented by a mixed-sign floating-point adder.

11. The non-transitory computer readable storage medium of claim 9 , wherein the floating-point subtractor is implemented by a mixed-sign floating-point adder.

12. The non-transitory computer readable storage medium of claim 8 , wherein the multiplexing and sign-correction logic is configured to:
generate the sum (A+B) of the two floating-point numbers (A, B) from one of the first result and the second result; and
generate the difference (A-B) of the two floating-point numbers (A, B) from the other of the first result and the second result.

13. The non-transitory computer readable storage medium of claim 8 , wherein the multiplexing and sign-correction logic is configured to correct a sign of the first result and a sign of the second result based on the sign of each of the two floating-point numbers (A, B).

14. The non-transitory computer readable storage medium of claim 12 , wherein the multiplexing and sign-correction logic is configured to correct a sign of the first result and a sign of the second result based on the sign of each of the two floating-point numbers (A, B).

15. A non-transitory computer-readable storage medium, having stored thereon computer program code configured to cause one or more processors to perform, when the computer program code is run on the one or more processors, a method of processing a computer-readable description of an integrated circuit to generate a representation of the integrated circuit, the method comprising:
receiving the computer-readable description of the integrated circuit;
identifying, in the computer-readable description of the integrated circuit, a description of one or more functional blocks for calculating a sum and difference of two floating-point numbers, each of the floating point numbers having a sign; and
generating the representation of the integrated circuit, wherein said one or more functional blocks are represented, in the representation of the integrated circuit, as a circuit comprising:
an input, configured to receive the two floating-point numbers;
a same-sign floating-point adder, configured to calculate a sum of absolute values of the two floating-point numbers, to produce a first result;
a floating-point subtractor, configured to calculate a difference of the absolute values of the two floating-point numbers, to produce a second result; and
multiplexing and sign-correction logic, configured to generate the sum of the two floating-point numbers and the difference of the two floating-point numbers based on: the first result, the second result, and the sign of each of the floating-point numbers,
wherein the same-sign floating-point adder is implemented in fixed function circuitry configured to add together floating-point numbers having the same sign, and wherein the same-sign floating-point adder does not include circuitry configured to add together numbers having different signs.

16. The non-transitory computer readable storage medium of claim 15 , wherein the floating-point subtractor is implemented in fixed function circuitry.

17. The non-transitory computer readable storage medium of claim 15 , wherein the floating-point subtractor is implemented by a mixed-sign floating-point adder.

18. The non-transitory computer readable storage medium of claim 16 , wherein t

Assignees

• Imagination Tech Ltd

Inventors

• Elliott Sam

Classifications

• G06F7/485 Primary

  Adding; Subtracting {(G06F7/4833, G06F7/4836 take precedence)} · CPC title

• G06F7/575 Primary

  Basic arithmetic logic units, i.e. devices selectable to perform either addition, subtraction or one of several logical operations, using, at least partially, the same circuitry · CPC title

• G06F7/74

  Selecting or encoding within a word the position of one or more bits having a specified value, e.g. most or least significant one or zero detection, priority encoders {(with shifting G06F5/01)} · CPC title

• G06F7/50

  Adding; Subtracting (G06F7/483 - G06F7/491, G06F7/544 - G06F7/556 take precedence) · CPC title

• G06F7/57

  Arithmetic logic units [ALU], i.e. arrangements or devices for performing two or more of the operations covered by groups G06F7/483 – G06F7/556 or for performing logical operations {(G06F7/49, G06F7/491 take precedence)} · CPC title