Fully implanted, wireless, flexible CMOS surface recording device

Patent metadata

Field	Value
Publication number	US-11607538-B2
Application number	US-201816604348-A
Country	US
Kind code	B2
Filing date	Apr 10, 2018
Priority date	Apr 10, 2017
Publication date	Mar 21, 2023
Grant date	Mar 21, 2023

Abstract

A fully implanted integrated, wireless, flexible CMOS chip for long-term recording and stimulation of the brain in vivo and methods of manufacturing thereof are provided. The chip is an entire biocompatible system and can include the dense surface electrode array, the underlying CMOS integrated circuit architecture, integrated wireless powering and telemetry. Furthermore, miniaturization through manufacturing, permits implantation of the chip under the skull and other regions of interest with no wires or connections. Furthermore, these devices and systems can operate under a dual modality such as to be able to record and stimulate the surface of the brain and/or tissue in which they have been implanted.

First claim

The invention claimed is:

1. An implantable neural recording and stimulation device comprising:
a flexible and thinned complementary metal-oxide-semiconductor (CMOS) chip configured to be positioned on a pial surface of a brain; and
an array of electrodes integrated into the CMOS chip configured to at least one of record or stimulate one or more analog signals from each of the electrodes.

2. The device of claim 1 , further comprising power harvesting circuitry configured to power the CMOS chip.

3. The device of claim 1 , further comprising a microcontroller coupled to the electrodes and configured to control the recording or stimulating of the one or more analog signals.

4. The device of claim 1 , further comprising one or more analog-to-digital (ADC) converters coupled to the array of electrodes and configured to digitize the one or more analog signals.

5. The device of claim 1 , further comprising:
a multiplexer configured to combine the one or more analog signals into a single analog signal; and
an analog to digital converter (ADC) coupled to the multiplexer and configured to digitize the single analog signal.

6. The device of claim 5 , wherein the ADC is a Successive-Approximation-Register (SAR) ADC.

7. The device of claim 5 , further comprising one or more amplifiers coupled to the electrodes and the multiplexer.

8. The device of claim 1 , further comprising a first set of antennas integrated into the CMOS chip and configured to receive power.

9. The device of claim 8 , further comprising a second set of antennas integrated into the CMOS chip and configured to receive and transmit one or more digital signals.

10. The device of claim 9 , wherein the first set of antennas and the second set of antennas operate at least two decades apart in frequency to reduce interference.

11. The device of claim 1 , wherein the CMOS chip is configured to have a thickness of 10 μm or less.

12. The device of claim 1 , wherein the electrodes are deposited with a HfO2 composition.

13. The device of claim 1 , further comprising an antialiasing filter coupled to the electrodes.

14. The device of claim 1 , wherein a back side of the device is passivated with parylene, silicon dioxide, or both.

15. A system for neural recording and stimulation, comprising:
an implantable neural recording and stimulation device comprising:
a flexible and thinned complementary metal-oxide-semiconductor (CMOS) chip configured to be positioned on a pial surface of a brain; and
an array of electrodes integrated into the CMOS chip configured to at least one of record or stimulate one or more analog signals from each of the electrodes;

external relay circuitry communicatively coupled to the implantable neural recording and stimulation device and configured to wirelessly power and transmit one or more signals from the implantable neural recording and stimulation device; and
a hardware processor communicatively coupled to the external relay circuitry and configured to process the transmitted one or more signals.

16. The system of claim 15 , wherein the external relay circuitry comprises a transceiver configured to transmit one or more signals from the implantable neural recording and stimulation device.

17. The system of claim 15 , wherein the external relay circuitry further comprises a controller configured to control the implantable neural recording and stimulation device.

18. The system of claim 17 , wherein the controller is configured to select an operation mode for one or more blocks of electrodes contained in the array of electrodes.

19. The system of claim 18 , wherein the selected operation mode is a stimulation mode and wherein the controller generates one or more commands for patterned stimulation using the one or more blocks of electrodes.

20. The system of claim 18 , wherein the selected operation mode is a sensing mode using the one or more blocks of electrodes.

21. The system of claim 15 , wherein the hardware processor is configured to detect one or more multi-neuronal events and compute a set of associated parameters.

22. The system of claim 21 , wherein the hardware processor is further configured to generate clusters of the set of parameters and identify the one or more detected multi-neuronal events.

Assignees

• Univ Columbia

Inventors

• Shepard Kenneth
• Tsai David
• Zeng Nanyu
• Jung Taesung

Classifications

• A61N1/0534 Primary

  Electrodes for deep brain stimulation · CPC title

• A61N1/3787

  from an external energy source · CPC title

• A61B5/0031 Primary

  Implanted circuitry · CPC title

• A61B2562/046

  in a matrix array · CPC title

• A61N1/37264

  Changing the program; Upgrading firmware · CPC title