Array substrate and display device

Patent metadata

Field	Value
Publication number	US-11605689-B2
Application number	US-201916975241-A
Country	US
Kind code	B2
Filing date	Oct 30, 2019
Priority date	Oct 30, 2019
Publication date	Mar 14, 2023
Grant date	Mar 14, 2023

Abstract

An array substrate and a display device. The array substrate includes a base substrate, a first electrode, a first insulating layer and a second electrode. The first electrode is on the base substrate; the first insulating layer is on a side of the first electrode away from the base substrate; the second electrode is on a side of the first insulating layer away from the first electrode. The second electrode is provided with a first through-hole and a slit communicated with the first through-hole and extending from the first through-hole to an edge of the second electrode, and an orthographic projection of the first electrode on the base substrate completely falls within an orthographic projection of the second electrode, the first through-hole and the slit on the base substrate. At this time, the first electrode, the second electrode, and the first insulating layer can constitute a capacitor.

First claim

The invention claimed is:

1. An array substrate, comprising:
a base substrate;
a first electrode on the base substrate;
a first insulating layer on a side of the first electrode away from the base substrate; and
a second electrode on a side of the first insulating layer away from the first electrode,
wherein the second electrode is provided with a first through-hole, and a slit communicated with the first through-hole and extending from the first through-hole to an edge of the second electrode, and an orthographic projection of the first electrode on the base substrate completely falls within an orthographic projection of the second electrode, the first through-hole and the slit on the base substrate.

2. The array substrate according to claim 1 , further comprising:
a second insulating layer on a side of the second electrode away from the base substrate; and
a connection electrode,
wherein the first insulating layer is provided with a second through-hole exposing the first electrode, the second insulating layer is partially located in the first through-hole and forms a third through-hole separated from the second electrode in the first through-hole, an orthographic projection of the third through-hole on the base substrate at least partially overlaps with an orthographic projection of the second through-hole on the base substrate, and the connection electrode is located in the second through-hole and in the third through-hole, and connected to the first electrode.

3. The array substrate according to claim 2 , further comprising:
an active layer on the base substrate;
a gate insulating layer on a side of the active layer away from the base substrate;
a first conductive layer on a side of the gate insulating layer away from the active layer; and
a second conductive layer,
wherein the first conductive layer comprises the first electrode, the first insulating layer is on a side of the first conductive layer away from the gate insulating layer, the second conductive layer is on a side of the first insulating layer away from the first conductive layer, and the second conductive layer comprises the second electrode.

4. The array substrate according to claim 1 , wherein the slit has an extending direction, and a length of the slit in the extending direction is in a range from 1 μm to 30 μm.

5. The array substrate according to claim 1 , wherein the slit has an extending direction, and a width of the slit in a direction perpendicular to the extending direction is in a range from 0.01 μm to 20 μm.

6. The array substrate according to claim 1 , further comprising:
an active layer on the base substrate;
a gate insulating layer on a side of the active layer away from the base substrate;
a first conductive layer on a side of the gate insulating layer away from the active layer; and
a second conductive layer,
wherein the first conductive layer comprises the first electrode, the first insulating layer is on a side of the first conductive layer away from the gate insulating layer, the second conductive layer is on a side of the first insulating layer away from the first conductive layer, and the second conductive layer comprises the second electrode.

7. The array substrate according to claim 6 , further comprising:
a third conductive layer on a side of the second insulating layer away from the second electrode;
a gate line in the first conductive layer and extending in a first direction; and
a data line in the third conductive layer and extending in a second direction,
wherein an extending direction of the slit is substantially parallel to the second direction.

8. The array substrate according to claim 7 , further comprising:
a planarization layer on a side of the third conductive layer away from the second insulating layer;
an anode on a side of the planarization layer away from the third conductive layer;
an organic light emitting layer on a side of the anode away from the planarization layer; and
a cathode on a side of the organic light emitting layer away from the anode.

9. The array substrate according to claim 1 , further comprising:
a first thin film transistor, comprising a first gate electrode, a first source electrode and a first drain electrode;
a second thin film transistor, comprising a second gate electrode, a second source electrode and a second drain electrode;
a third thin film transistor, comprising a third gate electrode, a third source electrode and a third drain electrode;
a fourth thin film transistor, comprising a fourth gate electrode, a fourth source electrode and a fourth drain electrode;
a fifth thin film transistor, comprising a fifth gate electrode, a fifth source electrode and a fifth drain electrode;
a sixth thin film transistor, comprising a sixth gate electrode, a sixth source electrode and a sixth drain electrode; and
a seventh thin film transistor, comprising a seventh gate electrode, a seventh source electrode and a seventh drain electrode,
wherein the first gate electrode of the first thin film transistor is connected to the third drain electrode of the third thin film transistor and the fourth drain electrode of the fourth thin film transistor, the first source electrode of the first thin film transistor is connected to the second drain electrode of the second thin film transistor and the fifth drain electrode of the fifth thin film transistor, and the first drain electrode of the first thin film transistor is connected to the third source electrode of the third thin film transistor and the sixth source electrode of the sixth thin film transistor,
the first electrode is connected to the first gate electrode of the first thin film transistor and the third drain electrode of the third thin film transistor, and the second electrode is configured to be connected to a power supply line.

10. The array substrate according to claim 9 , wherein an orthographic projection of the first through-hole on the base substrate at least partially overlaps with an orthographic projection of the first gate electrode of the first thin film transistor on the base substrate.

11. The array substrate according to claim 9 , wherein the first electrode and the first gate electrode of the first thin film transistor are the same structure.

12. The array substrate according to claim 1 , wherein the first electrode comprises a rectangle shape.

13. The array substrate according to claim 12 , wherein the first electrode comprises a rectangle shape with chamfers at corners.

14. A display device, comprising the array substrate according to claim 1 .

15. The array substrate according to claim 1 , wherein the first electrode, the second electrode, and the first insulating layer between the first electrode and the second electrode constitute a capacitor.

Assignees

• Chengdu Boe Optoelect Tech Co
• Boe Technology Group Co Ltd
• Boetechnology Group Co Ltd

Inventors

• Yuan Changlong
• Wang Benlian
• Xu Yingsong
• Cao Xilei

Classifications

• H10K59/1216 Primary

  the pixel elements being capacitors · CPC title

• G09G2300/08

  Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements · CPC title

• H01G4/40

  Structural combinations of fixed capacitors with other electric elements, the structure mainly consisting of a capacitor, e.g. RC combinations · CPC title

• G09G3/3233

  with pixel circuitry controlling the current through the light-emitting element · CPC title

• H01G4/005

  Electrodes · CPC title