Apparatus, system and method for offloading data transfer operations between source and destination storage devices to a hardware accelerator

Patent metadata

Field	Value
Publication number	US-11604594-B2
Application number	US-202117390441-A
Country	US
Kind code	B2
Filing date	Jul 30, 2021
Priority date	Apr 12, 2019
Publication date	Mar 14, 2023
Grant date	Mar 14, 2023

Abstract

Provided are an apparatus, system and method for offloading data transfer operations between source and destination storage devices to a hardware accelerator. The hardware accelerator includes a memory space and control logic to receive, from a host processor, a command descriptor indicating at least one source storage device having transfer data to transfer to at least one destination storage device and a computational task to perform on the transfer data. The control logic sends read commands to the at least one source storage device to read the transfer data to at least one read buffer in the memory space and performs the computational task on the transfer data to produce modified transfer data. The control logic writes the modified transfer data to at least one write buffer in the memory space to cause the modified transfer data to be written to the at least one destination storage device.

First claim

What is claimed:

1. A hardware accelerator comprising:
a memory space to include read buffers and write buffers for a plurality of storage devices having respective storage device controllers, the plurality of storage devices coupled with and separate from the hardware accelerator; and
control logic to:
receive, from a host processor coupled with the hardware accelerator, a command descriptor that indicates a source storage device having data to modify and store to a destination storage device and a computational task to perform on the data, the source storage device and the destination storage device included in the plurality of storage devices;
send at least one read command to the source storage device to cause the source storage device to store the data in at least one read buffer in the memory space;
perform the computational task using the data stored in the at least one read buffer to modify the data; and
write the modified data to at least one write buffer in the memory space to cause the modified data to be stored to the destination storage device.

2. The hardware accelerator of claim 1 , comprising the command descriptor to also include:
a source pointer to source information in a host memory space of the host processor, the source information to indicate a source address location for the data maintained at the source storage device; and
a destination pointer to destination information in the host memory space, the destination information to indicate a destination address location to which the modified data is to be stored at the destination storage device.

3. The hardware accelerator of claim 2 , further comprising:
the source information to include a source entry for the source storage device, the source entry to indicate a source address range of the source storage device that stores the data; and
the destination information to include a destination entry for the destination storage device, the destination entry to indicate a destination address range of the destination storage device to which the modified data is to be stored at the destination storage device.

4. The hardware accelerator of claim 3 , further comprising the source entry to also include a source queue doorbell address for the source storage device and the destination entry to also include a destination queue doorbell address for destination storage device, wherein the control logic is further to:
write information to the source queue doorbell address indicated in the source entry to cause the source storage device to transfer the data stored in the source address range; and
write information to the destination queue doorbell address indicated in the destination entry to cause the modified data to be stored to the destination storage device.

5. The hardware accelerator of claim 1 , further comprising the control logic to
receive a configuration command from the host processor to extend a memory space of the host processor, wherein the read and the write buffers are configured in mapped addresses in the memory space, and wherein the mapped addresses in the memory space extends the memory space of the host processor.

6. The hardware accelerator of claim 1 , further comprising the control logic to receive, from the host processor, configuration commands, the configuration commands to cause the control logic to:
configure read and write buffers in the memory space; and
configure submission queues in the memory space, wherein the control logic adds the at least one read command to a first submission queue of the submission queues to cause the source storage device to transfer data to the read buffers and adds a write command to a second submission queue of the submission queues to cause the destination storage device to obtain the modified data from the write buffers to store the modified data to the destination storage device.

7. The hardware accelerator of claim 1 , the control logic comprises a field programmable gate array (FPGA).

8. The hardware accelerator of claim 1 , the control logic comprises an application specific integrated circuit (ASIC).

9. A system comprising:
dual in-line memory modules (DIMMs) to support a system memory space of a host processor;
a plurality of storage device having respective storage device controllers; and
a hardware accelerator that includes:
a memory space to include read buffers and write buffers for the plurality of storage devices; and
control logic to:
receive, from the host processor, a command descriptor that indicates a source storage device maintains data to modify, a destination storage device and a computational task to perform on the data, the source storage device and the destination storage device included in the plurality of storage devices;
send at least one read command to the source storage device to cause the source storage device to store the data in at least one read buffer in the memory space;
perform the computational task using the data stored in the at least one read buffer to modify the data; and
write the modified data to at least one write buffer in the memory space to cause the modified data to be stored to the destination storage device.

10. The system of claim 9 , comprising the command descriptor to also include:
a source pointer to source information in the system memory space of the host processor, the source information to indicate a source address location for the data maintained at the source storage device; and
a destination pointer to destination information in the system memory space of the host processor, the destination information to indicate a destination address location to which the modified data is to be stored at the destination storage device.

11. The system of claim 10 , further comprising:
the source information to include a source entry for the source storage device, the source entry to indicate a source address range of the source storage device that stores the data; and
the destination information to include a destination entry for the destination storage device, the destination entry to indicate a destination address range of the destination storage device to which the modified data is to be stored at the destination storage device.

12. The system of claim 11 , further comprising the source entry to also include a source queue doorbell address for the source storage device and the destination entry to also include a destination queue doorbell address for destination storage device, wherein the control logic is further to:
write information to the source queue doorbell address indicated in the source entry to cause the source storage device to transfer the data stored in the source address range; and
write information to the destination queue doorbell address indicated in the destination entry to cause the modified data to be stored to the destination storage device.

13. The system of claim 9 , further comprising the control logic to:
receive a configuration command from the host processor to extend the system memory space of the host processor, wherein the read and the write buffers are configured in mapped addresses in the memory space, and wherein the mapped addresses in the memory space extends the system memory space of the host processor.

14. The system claim 9 , further comprising the control logic to receive, from the host processor, configuration commands, the configuration commands to cause the control logic to:
configure read and write buffers in the memory space; and
configure submission queues in the memory space, wherein the control logic adds the at least one read command to a first submission queue of the submiss

Assignees

• Intel Corp

Inventors

• Narayanan Divya
• Khan Jawad B
• Nelson Michael D
• Pethe Akshay G

Classifications

• G06F3/0647 Primary

  Migration mechanisms · CPC title

• G06F3/0656

  Data buffering arrangements · CPC title

• G06F3/0646 Primary

  Horizontal data movement in storage systems, i.e. moving data in between storage devices or systems · CPC title

• G06F3/0604

  Improving or facilitating administration, e.g. storage management · CPC title

• G06F3/0683

  Plurality of storage devices · CPC title