Memory extension system and method

Patent metadata

Field	Value
Publication number	US-9811497-B2
Application number	US-201414584698-A
Country	US
Kind code	B2
Filing date	Dec 29, 2014
Priority date	Sep 25, 2013
Publication date	Nov 7, 2017
Grant date	Nov 7, 2017

Abstract

A memory extension system and method are provided. The system includes a processor, an extended memory, an extended chip, and multiple processor installation positions, where a memory installation position is provided in each processor installation position; the multiple processor installation positions are connected through a QuickPath Interconnect (QPI) interface, the processor is installed in at least one processor installation position, and at least one of the other processor installation positions is used as an extended installation position; the extended chip is installed in at least one extended installation position; and the extended memory is installed in a memory installation position. In this memory extension system, an extended chip is installed in another processor installation position, so that an existing processor can access an extended memory of the extended chip by using the extended chip. Thereby, a memory capacity of the existing processor increases while a processing capability does not increase.

First claim

What is claimed is:

1. A memory extension system, comprising:
a processor, an extended memory, an extended chip, and multiple processor installation positions, wherein:
each of the processor installation positions is connected to a corresponding memory installation position;
the multiple processor installation positions are connected through QuickPath Interconnect (QPI) interfaces, the processor is installed in at least one processor installation position, and at least one of the other processor installation positions is used as an extended installation position;
the extended chip is of a different type than the processor, the extended chip is installed in at least one extended installation position, and the extended chip has a unique identification number;
the extended memory is installed in a memory installation position that is connected to the extended chip, and all addresses of the extended memory are within an address space of the processor; and
the extended chip comprises:
a QPI interface module connected to a QPI interface in the extended installation position in which the extended chip is located, and configured to receive a packet that is sent by the processor using a QPI protocol;
a processing device configured to convert the packet from the QPI protocol into a memory interface protocol and send the packet to a memory interface module; and
the memory interface module connected to the extended memory in the memory installation position in the extended installation position in which the extended chip is located, and configured to read data from or write data into the extended memory according to the packet obtained after the protocol conversion, and send the read data to the processing device;
wherein the processing device is further configured to convert the read data from the memory interface protocol into the QPI protocol and send the data to the QPI interface module, and the QPI interface module is further configured to send the data obtained after the protocol conversion through the QPI interface in the extended installation position in which the extended chip is located.

2. The system according to claim 1 , wherein one or more pins of the extended chip are compatible with one or more corresponding pins of the processor.

3. The system according to claim 1 , wherein the processor is configured to:
generate an identification number query instruction;
send the identification number query instruction through a QPI interface in the processor installation position in which the processor is located;
receive an identification number through the QPI interface in the processor installation position in which the processor is located;
determine whether the identification number is an identification number of the extended chip; and
when the identification number is an identification number of the extended chip, configure a memory controller for the extended chip, and allocate, from the address space of the processor, a memory address corresponding to the extended memory that is connected to the extended chip.

4. The system according to claim 3 , wherein the processor is further configured to:
generate the packet for reading data or writing data in accordance with the QPI protocol;
send the packet through the QPI interface in the processor installation position in which the processor is located; and
receive, through the QPI interface in the processor installation position in which the processor is located, the data that is read by the extended chip according to the packet.

5. The system according to claim 4 , wherein the extended chip is configured to:
receive the identification number query instruction through a QPI interface in the extended installation position in which the extended chip is located;
acquire the identification number of the extended chip according to the identification number query instruction; and
send the acquired identification number through the QPI interface in the extended installation position in which the extended chip is located.

6. A memory extension method, comprising:
generating, by a processor, an identification number query instruction, and sending the identification number query instruction through a QuickPath Interconnect (QPI) interface in a processor installation position in which the processor is located;
receiving, by an extended chip, the identification number query instruction through a QPI interface in a processor installation position in which the extended chip is located, acquiring an identification number of the extended chip according to the identification number query instruction, and sending the acquired identification number through the QPI interface in the processor installation position in which the extended chip is located, wherein the extended chip is of a different type than the processor;
receiving, by the processor, the identification number through the QPI interface in the processor installation position in which the processor is located, determining whether the identification number is an identification number of the extended chip, and when the identification number is an identification number of the extended chip, configuring a memory controller for the extended chip, and allocating, from address space of the processor, a memory address corresponding to an extended memory that is connected to the extended chip;
generating, by the processor, a packet for reading data or writing data in accordance with a QPI protocol, and sending the packet through the QPI interface in the processor installation position in which the processor is located;
receiving, by the extended chip, the packet through the QPI interface in the processor installation position in which the extended chip is located, after the packet is converted from the QPI protocol into a memory interface protocol, reading data from or writing data into the extended memory that is connected to the extended chip according to the packet obtained after the protocol conversion, and sending, after the read data is converted from the memory interface protocol into the QPI protocol, the read data through the QPI interface in the processor installation position in which the extended chip is located; and
receiving, by the processor, the data obtained after the protocol conversion through the QPI interface in the processor installation position in which the processor is located.

7. The method according to claim 6 , further comprising:
determining, by the processor, whether the identification number query instruction has been sent to all QPI interfaces in the processor installation position in which the processor is located; and
if it is determined that the identification number query instruction has not been sent to all QPI interfaces in the processor installation position in which the processor is located, sending, by the processor, the identification number query instruction to a QPI interface to which the identification number query instruction has not been sent.

Assignees

• Huawei Tech Co Ltd

Inventors

• Li Yansong
• Zheng Yulin

Classifications

• G06F13/4027

  using bus bridges (G06F13/4022 takes precedence) · CPC title

• G06F13/4234 Primary

  being a memory bus · CPC title