Differential cascode amplifier arrangement with reduced common mode gate RF voltage

Patent metadata

Field	Value
Publication number	US-11601098-B2
Application number	US-202117214712-A
Country	US
Kind code	B2
Filing date	Mar 26, 2021
Priority date	Mar 26, 2021
Publication date	Mar 7, 2023
Grant date	Mar 7, 2023

Abstract

Methods and devices for reducing gate node instability of a differential cascode amplifier are presented. Ground return loops, and therefore corresponding parasitic inductances, are eliminated by using voltage symmetry at nodes of two cascode amplification legs of the differential cascode amplifier. Series connected capacitors are coupled between gate nodes of pairs of cascode amplifiers of the two cascode amplification legs so to create a common node connecting the two capacitors. In order to reduce peak to peak voltage variation at the common node under large signal conditions, a shunting capacitor is connected to the common node.

First claim

The invention claimed is:

1. A differential radio frequency (RF) cascode amplification circuit comprising:
a first cascode amplification leg comprising a first input transistor and a first group of cascode transistors including a first output transistor, wherein the first cascode amplification leg is configured to amplify a first input RF signal of a differential RF input signal;
a second cascode amplification leg comprising a second input transistor and a second group of cascode transistors including a second output transistor, wherein the second cascode amplification leg is configured to amplify a second input RF signal of the differential RF input signal; and
at least one capacitive coupling arrangement coupled between a first gate node of a first cascode transistor of the first group of cascode transistors and a second gate node of a second cascode transistor of the second group of cascode transistors,
wherein:
the at least one capacitive coupling arrangement comprises a shunting capacitor; the shunting capacitor comprises two parallel capacitors of a same value,
each of the two parallel capacitors comprises a top conductive plate and a bottom conductive plate,
the top conductive plate of a first capacitor of the two parallel capacitors is connected to the bottom conductive plate of a second capacitor of the two parallel capacitors, and
the bottom conductive plate of the first capacitor of the two parallel capacitors is connected to the top conductive plate of the second capacitor of the two parallel capacitors.

2. The differential radio frequency (RF) cascode amplification circuit of claim 1 , wherein the first and the second cascode amplification legs are coupled between a fixed supply voltage and a reference ground.

3. The differential radio frequency (RF) cascode amplification circuit of claim 1 , wherein the first and the second cascode amplification legs are coupled between a variable supply voltage and a reference ground.

4. The differential radio frequency (RF) cascode amplification circuit of claim 3 , wherein the variable supply voltage varies under control of an external control signal.

5. The differential radio frequency (RF) cascode amplification circuit of claim 1 , wherein the first and second input transistors and the first and second groups of cascode transistors are metal-oxide-semiconductor (MOS) field effect transistors (FETs), or complementary metal-oxide-semiconductor (CMOS) field effect transistors (FETs).

6. The differential radio frequency (RF) cascode amplification circuit of claim 5 , wherein said transistors are fabricated using one of: a) silicon-on-insulator (SOI) technology, and b) silicon-on-sapphire technology (SOS).

7. An electronic module comprising the differential radio frequency (RF) cascode amplification circuit of claim 1 .

8. A method, comprising using of the electronic module of claim 7 in one or more electronic systems comprising: a) a sensor, b) a cellular telephone, c) a laptop or personal computer, d) a workstation, e) a test equipment, f) an edge server, g) a vehicle, h) a medical device, or i) other electronic systems.

9. A differential radio frequency (RF) cascode amplification circuit comprising:
a first cascode amplification leg comprising a first input transistor and a first group of cascode transistors including a first output transistor, wherein the first cascode amplification leg is configured to amplify a first input RF signal of a differential RF input signal;
a second cascode amplification leg comprising a second input transistor and a second group of cascode transistors including a second output transistor, wherein the second cascode amplification leg is configured to amplify a second input RF signal of the differential RF input signal; and
at least one capacitive coupling arrangement coupled between a first gate node of a first cascode transistor of the first group of cascode transistors and a second gate node of a second cascode transistor of the second group of cascode transistors,
wherein the at least one capacitive coupling arrangement comprises a shunting capacitor, and
wherein the at least one capacitive coupling arrangement further comprises a first capacitor connected between the first gate node and the shunting capacitor, and a second capacitor connected between the second gate node and the shunting capacitor.

10. The differential radio frequency (RF) cascode amplification circuit of claim 9 , wherein:
the first capacitor and the second capacitor are series-connected capacitors of a same capacitance.

11. The differential radio frequency (RF) cascode amplification circuit of claim 10 , wherein:
a capacitance of the shunting capacitor is configured to attenuate a peak to peak voltage at an intermediate gate node that is common to the shunting capacitor, the first capacitor and the second capacitor.

12. The differential radio frequency (RF) cascode amplification circuit of claim 10 , wherein:
a capacitance of the shunting capacitor is in range from about two times to about ten times the capacitance of the first capacitor.

13. The differential radio frequency (RF) cascode amplification circuit of claim 10 , wherein:
a capacitance of the shunting capacitor is about five times the capacitance of the first capacitor.

14. The differential radio frequency (RF) cascode amplification circuit of claim 10 , wherein:
the same capacitance is configured to provide, at a frequency of operation of the differential RF input signal, respective non-zero impedances coupled to the first and second gate nodes.

15. The differential radio frequency (RF) cascode amplification circuit of claim 14 , wherein the respective non-zero impedances allow
the first gate node to float with respect to an RF signal coupled to the first cascode transistor that is based on the first input RF signal, and
the second gate node to float with respect to an RF signal coupled to the second cascode transistor that is based on the second input RF signal.

16. The differential radio frequency (RF) cascode amplification circuit of claim 14 , wherein the respective non-zero impedances provide a distribution of RF voltages output by respective first and second cascode amplification legs across respective transistors of said amplification legs.

17. The differential radio frequency (RF) cascode amplification circuit of claim 16 , wherein said distribution is such that a drain-to-source voltage across each transistor of a respective amplification leg is about equal.

18. A differential radio frequency (RF) cascode amplification circuit comprising:
a first cascode amplification leg comprising a first input transistor and a first group of cascode transistors including a first output transistor, wherein the first cascode amplification leg is configured to amplify a first input RF signal of a differential RF input signal;
a second cascode amplification leg comprising a second input transistor and a second group of cascode transistors including a second output transistor, wherein the second cascode amplification leg is configured to amplify a second input RF signal of the differential RF input signal; and
at least one capacitive coupling arrangement coupled between a first gate node of a first cascode transistor of the first group of cascode transistors and a second gate node of a second cascode transistor of the second group of cascode transistors,
wherein the at least one capacitive coupling arrangement comprises a shunting capacitor and;
wherein the at least one capacitive coupling arrangement comprises a plurality of

Assignees

• Psemi Corp

Inventors

• Nobbe Dan William

Classifications

• H03F2200/267

  A capacitor based passive circuit, e.g. filter, being used in an amplifying circuit · CPC title

• H03F1/3211 Primary

  in differential amplifiers · CPC title

• H03F1/223

  with MOSFET's · CPC title

• H03F2203/45638

  the LC comprising one or more coils · CPC title

• H03F3/45179

  using MOSFET transistors as the active amplifying circuit (H03F3/45278 takes precedence) · CPC title