Resistance variable device with chalcogen-containing layer

Patent metadata

Field	Value
Publication number	US-11600772-B2
Application number	US-202017014587-A
Country	US
Kind code	B2
Filing date	Sep 8, 2020
Priority date	Dec 25, 2019
Publication date	Mar 7, 2023
Grant date	Mar 7, 2023

Abstract

A resistance variable device of an embodiment includes a stack arranged between a first electrode and a second electrode and including a resistance variable layer and a chalcogen-containing layer. The chalcogen-containing layer contains a material having a composition represented by a general formula: C1xC2yAz, where C1 is at least one element selected from Sc, Y, Zr, and Hf, C2 is at least one element selected from C, Si, Ge, B, Al, Ga, and In, A is at least one element selected from S, Se, and Te, and x, y, and z are numbers representing atomic ratios satisfying 0<x<1, 0<y<1, 0<z<1, and x+y+z=1, and when an oxidation number of the element C1 is set to a, and an oxidation number of the element C2 is set to b, the atomic ratio x of the element C1 satisfies x≤(3−(3+b)×y−z)/(3+a).

First claim

What is claimed is:

1. A resistance variable device, comprising:
a first electrode;
a second electrode; and
a stack arranged between the first electrode and the second electrode and including a resistance variable layer and a chalcogen-containing layer, wherein
the resistance variable layer constitutes a magnetoresistive random access memory,
the chalcogen-containing layer which is a switch layer, contains a material having a composition represented by a general formula:
C1 x C2 y A z

wherein C1 is at least one element selected from the group consisting of Zr and Hf, C2 is at least one element selected from the group consisting of C, Si, Ge, B, Al, Ga, and In, A is at least one element selected from the group consisting of S, Se, and Te, and x, y, and z are numbers representing atomic fractions satisfying 0<x<1, 0<y<1, 0<z<1, and x+y+z=1, and when an oxidation number of the element C1 is set to a, and an oxidation number of the element C2 is set to b, the atomic fraction x of the element C1 satisfies x≤(3−(3+b)×y−z)/(3+a), and
the chalcogen-containing layer further contains N.

2. The device according to claim 1 , wherein
x in the general formula is 0.01 or more and 0.32 or less, y in the general formula is 0.1 or more, and z in the general formula is 0.1 or more.

3. The device according to claim 1 , wherein
the chalcogen-containing layer has an amorphous structure.

4. The device according to claim 1 , wherein
the chalcogen-containing layer is configured to transit between a high-resistance state and a low-resistance state, and
the chalcogen-containing layer has an amorphous structure in both the high-resistance state and the low-resistance state.

5. The device according to claim 1 , wherein
the C2 is at least one element selected from the group consisting of C, B, Ga, and In.

6. The device according to claim 1 , wherein
the resistance variable layer includes a magnetoresistive random access memory layer, and
the chalcogen-containing layer is in contact with one of the first electrode or the second electrode, and in contact with the magnetoresistive random access memory layer.

7. A resistance variable device, comprising:
a first electrode;
a second electrode; and
a stack arranged between the first electrode and the second electrode and including a resistance variable layer and a chalcogen-containing layer, wherein
the resistance variable layer constitutes a magnetoresistive random access memory, and
the chalcogen-containing layer which is a switch layer, contains a material having a composition represented by a general formula:
C1 x C2 y A z N w

wherein C1 is at least one element selected from the group consisting of Sc, Y, Zr and Hf, C2 is at least one element selected from the group consisting of C, Si, Ge, B, Al, Ga, and In, A is at least one element selected from the group consisting of S, Se, and Te, and x, y, z, and w are numbers representing atomic fractions satisfying 0<x<1, 0<y<1, 0<z<1, 0<w<1, and x+y+z+w=1, and when an oxidation number of the element C1 is set to a, and an oxidation number of the element C2 is set to b, the atomic fraction x of the element C1 satisfies x≤(3−(3+b)×y−z)/(3+a), and the atomic fraction w of N satisfies w<(a−(a−b)×y−(a+2)×z)/(3+a).

8. The device according to claim 7 , wherein
x in the general formula is 0.01 or more and 0.32 or less, y in the general formula is 0.1 or more, z in the general formula is 0.1 or more, and w in the general formula is 0.01 or more and 0.48 or less.

9. The device according to claim 7 , wherein
the chalcogen-containing layer has an amorphous structure.

10. The device according to claim 7 , wherein
the chalcogen-containing layer is configured to transit between a high-resistance state and a low-resistance state, and
the chalcogen-containing layer has an amorphous structure in both the high-resistance state and the low-resistance state.

11. The device according to claim 7 , wherein
the C2 is at least one element selected from the group consisting of C, B, Ga, and In.

12. The device according to claim 7 , wherein
the resistance variable layer includes a magnetoresistive random access memory layer, and
the chalcogen-containing layer is in contact with one of the first electrode or the second electrode, and in contact with the magnetoresistive random access memory layer.

13. A resistance variable device, comprising:
a first electrode;
a second electrode; and
a stack arranged between the first electrode and the second electrode and including a resistance variable layer and a chalcogen-containing layer, wherein
the resistance variable layer constitutes a magnetoresistive random access memory,
the chalcogen-containing layer which is a switch layer, contains at least one element C1 selected from the group consisting of Zr and Hf, at least one element C2 selected from the group consisting of C, Si, Ge, B, Al, Ga, and In, and at least one element A selected from the group consisting of S, Se, and Te, and
the chalcogen-containing layer further contains N.

14. The device according to claim 13 , wherein
the chalcogen-containing layer has an amorphous structure.

15. The device according to claim 13 , wherein
the chalcogen-containing layer is configured to transit between a high-resistance state and a low-resistance state, and
the chalcogen-containing layer has an amorphous structure in both the high-resistance state and the low-resistance state.

16. The device according to claim 13 , wherein
the C2 is at least one element selected from the group consisting of C, B, Ga, and In.

17. The device according to claim 13 , wherein
the resistance variable layer includes a magnetoresistive random access memory layer, and
the chalcogen-containing layer is in contact with one of the first electrode or the second electrode, and in contact with the magnetoresistive random access memory layer.

Assignees

• Kioxia Corp

Inventors

• Kawai Hiroki
• Komatsu Katsuyoshi
• Daibou Tadaomi
• Tokuhira Hiroki
• Yoshikawa Masatoshi
• Ito Yuichi

Classifications

• H10N70/8825

  Selenides, e.g. GeSe · CPC title

• H10N70/8828

  Tellurides, e.g. GeSbTe · CPC title

• H10N70/25

  based on bulk electronic defects, e.g. trapping of electrons · CPC title

• H10B61/10 Primary

  comprising components having two electrodes, e.g. diodes or MIM elements · CPC title

• H10N70/841 Primary

  Electrodes · CPC title