Semiconductor memory device

Patent metadata

Field	Value
Publication number	US-11600620-B2
Application number	US-202117353398-A
Country	US
Kind code	B2
Filing date	Jun 21, 2021
Priority date	Jan 7, 2020
Publication date	Mar 7, 2023
Grant date	Mar 7, 2023

Abstract

A semiconductor memory device is provided. The device includes a substrate including a cell region and a peripheral region; a plurality of lower electrodes disposed on the substrate in the cell region; a dielectric layer disposed on the plurality of lower electrodes; a metal containing layer disposed on the dielectric layer; a silicon germanium layer disposed on and electrically connected to the metal containing layer; a conductive pad disposed on and electrically connected to the silicon germanium layer; and an upper electrode contact plug disposed on and electrically connected to the conductive pad; The conductive pad extends from the upper electrode contact plug towards the peripheral region in a first direction, and the silicon germanium layer includes an edge portion that extends past the conductive pad in the first direction.

First claim

What is claimed is:

1. A method of manufacturing a semiconductor device, the method comprising:
providing a substrate including a cell region and a peripheral region;
forming a plurality of lower electrodes on the substrate in the cell region;
forming a dielectric layer on the plurality of lower electrodes;
forming a metal containing layer on the dielectric layer;
forming a silicon germanium layer that is electrically connected to the metal containing layer on the metal containing layer;
forming an interlayered insulating layer on a top surface and a side surface of the silicon germanium layer;
forming an etch mask pattern on the interlayered insulating layer, the etch mask pattern defining an opening that overlaps the cell region;
performing an etch process using the etch mask pattern to form recess in an upper portion of the silicon germanium layer; and
forming a conductive pad that is disposed in the recess, and is in contact with the top surface of the silicon germanium layer and the side surface of the silicon germanium layer.

2. The method of claim 1 , wherein a bottom surface of the recess of the silicon germanium layer is vertically spaced apart from the plurality of lower electrodes.

3. The method of claim 1 , wherein a width of the silicon germanium layer is greater than a width of the conductive pad.

4. The method of claim 1 , wherein a first surface of the silicon germanium layer, a second surface of the silicon germanium layer, and a side surface of the silicon germanium layer between the first surface and the second surface of the silicon germanium layer form a step structure.

5. The method of claim 1 , further comprising:
after forming the conductive pad, forming a second interlayered insulating layer on the top surface of the conductive pad and the top surface of the interlayered insulating layer;
forming a second etch mask pattern on the second interlayered insulating layer, the second etch mask pattern defining a second opening and a third opening, the second opening overlaps the cell region and the third opening overlaps the peripheral region;
performing an etch process using the second etch mask pattern to form an upper electrode contact hole in the cell region and a peripheral contact hole in the peripheral region, the peripheral contact hole being deeper than the upper electrode contact hole; and
filling the upper electrode contact hole and the peripheral contact hole with a conductive material to form an upper contact plug in the upper electrode contact hole and a peripheral contact plug in the peripheral contact hole.

6. The method of claim 1 , wherein the forming the conductive pad comprises:
forming a conductive layer filling the recess; and
planarizing a top surface of the conductive layer and a top surface of the interlayered insulating layer.

7. The method of claim 1 , wherein the forming the plurality of lower electrodes on the substrate in the cell region comprises:
forming a first mold structure on the substrate in the cell region and the peripheral region;
forming first electrode holes penetrating the first mold structure in the cell region;
filling the first electrode holes with a conductive material to form conductive pillars;
forming a second mold structure on the first mold structure in the cell region and the peripheral region;
forming second electrode holes penetrating the second mold structure in the cell region, each of the second electrode holes expose a top surface of conductive pillar; and
filling the second electrode holes with a conductive material to extend the conductive pillars.

8. The method of claim 7 , wherein the first mold structure comprises a first mold layer, a first supporting layer, a second mold layer, a second supporting layer, and a third mold layer, which are sequentially formed,
wherein the second mold structure comprises a fourth mold layer, a third supporting layer, a fifth mold layer, a fourth supporting layer, and a sixth mold layer, which are sequentially formed, and
wherein the method further comprises, after filling the second electrode holes with a conductive material to extend the conductive pillars, etching the sixth mold layer, the fifth mold layer, the fourth mold layer, the third mold layer, the second mold layer, the first mold layer sequentially and selectively.

9. The method of claim 1 , wherein an etch rate of the conductive pad is less than an etch rate of the interlayered insulating layer.

10. The method of claim 1 , further comprising:
forming a poly-silicon layer interposed between the silicon germanium layer, and the conductive pad; and
doping impurities to the poly-silicon layer.

11. A method of manufacturing a semiconductor device, the method comprising:
providing a substrate including a cell region and a peripheral region;
forming a plurality of lower electrodes on the substrate in the cell region;
forming a dielectric layer on the plurality of lower electrodes;
forming a metal containing layer on the dielectric layer;
forming a silicon germanium layer that is electrically connected to the metal containing layer on the metal containing layer;
forming a first interlayered insulating layer on a top surface and a side surface of the silicon germanium layer;
forming an etch mask pattern on the first interlayered insulating layer, the etch mask pattern defining a first opening and a second opening that overlaps the cell region;
performing an etch process using the etch mask pattern to form a first recess and a second recess in an upper portion of the silicon germanium layer;
forming a first conductive pad that is disposed in the first recess and a second conductive pad that is disposed in the second recess are in contact with a top surface of the silicon germanium layer and a side surface of the silicon germanium layer;
forming a second interlayered insulator covering the first conductive pad, the second conductive pad, and the silicon germanium layer in the cell region and the first interlayered insulating layer in the peripheral region; and
forming a first upper electrode contact plug penetrating the second interlayered insulator disposed on and electrically connected to the first conductive pad and a second upper electrode contact plug penetrating the second interlayered insulator disposed on and electrically connected to the second conductive pad.

12. The method of claim 11 , wherein a recess is formed in the first conductive pad and a recess is formed in the second conductive pad,
wherein the recess in the first conductive pad is filled by part of the first upper electrode contact plug, and
wherein the recess in the second conductive pad is filled by part of the second upper electrode contact plug.

13. The method of claim 11 , further comprising:
forming a poly-silicon layer between the silicon germanium layer, and both the first conductive pad and the second conductive pad.

14. The method of claim 11 , wherein the forming the plurality of lower electrodes on the substrate in the cell region comprises:
forming a first mold structure on the substrate in the cell region and the peripheral region;
forming first electrode holes penetrating the first mold structure in the cell region;
filling the first electrode holes with a conductive material to form conductive pillars;
forming a second mold structure on the first mold structure in the cell region and the peripheral region;
forming second electrode holes penetrating the second mold structure in the cell region, each of the second electrode holes expose a top surface of conductive pillar; and
filling the second electrode holes with a cond

Assignees

• Samsung Electronics Co Ltd

Inventors

• Han Sang-Il
• Han Sunghee
• Hwang Yoosang

Classifications

• H10B12/033

  the capacitor extending over the transistor · CPC title

• H10B12/31 Primary

  having a storage electrode stacked over the transistor · CPC title

• H10B12/315 Primary

  with the capacitor higher than a bit line · CPC title

• H10B12/03

  Making the capacitor or connections thereto · CPC title

• H10B12/01

  Manufacture or treatment · CPC title