Semiconductor structure and fabrication method thereof

Patent metadata

Field	Value
Publication number	US-11600619-B2
Application number	US-202017034129-A
Country	US
Kind code	B2
Filing date	Sep 28, 2020
Priority date	Oct 23, 2019
Publication date	Mar 7, 2023
Grant date	Mar 7, 2023

Abstract

A semiconductor structure and its fabrication method are provided in the present disclosure. The method includes providing a substrate, forming a plurality of fins on the substrate, and forming an isolation structure layer including a plurality of isolation structures on the substrate, each isolation structure being formed between adjacent fins. The method further includes forming a first opening by etching at least one isolation structure of the plurality of isolation structures and a portion of the substrate, and forming a power rail by filling the first opening with a conductive material, where a top surface of the power rail is lower than a top surface of the plurality of fins.

First claim

What is claimed is:

1. A method for fabricating a semiconductor structure, comprising:
providing a substrate;
forming a plurality of fins on the substrate;
forming an isolation structure layer including a plurality of isolation structures on the substrate, each isolation structure being formed between adjacent fins;
forming a first opening by etching at least one isolation structure of the plurality of isolation structures and a portion of the substrate, wherein a remaining portion of the at least one isolation structure of the plurality of isolation structures has a top surface lower than a top surface of the isolation structure layer; and
forming a power rail by filling the first opening with a conductive material, wherein a top surface of the power rail is lower than a top surface of the plurality of fins, lower than the top surface of the remaining portion of the at least one isolation structure of the plurality of isolation structures, and higher than a top surface of the substrate.

2. The method according to claim 1 , wherein:
the conductive material is made of a material including ruthenium, copper, graphene, or a combination thereof.

3. The method according to claim 1 , wherein:
the first opening is filled with the conductive material by an electrochemical deposition process.

4. The method according to claim 1 , wherein forming the first opening by etching the at least one isolation structure and the portion of the substrate includes:
etching the at least one isolation structure till a surface of the portion of the substrate is exposed to form a first trench; and
continuously etching the portion of the substrate along the first trench to form the first opening.

5. The method according to claim 1 , wherein:
forming the first opening by etching the at least one isolation structure and the portion of the substrate includes a plasma dry etching process.

6. The method according to claim 1 , wherein:
after forming the power rail, a metal layer is formed on the power rail.

7. The method according to claim 1 , wherein:
a top surface of the isolation structure layer is coplanar with the top surface of the plurality of fins.

8. A method for fabricating a semiconductor structure, comprising:
providing a substrate;
forming a plurality of fins on the substrate;
forming an isolation structure layer including a plurality of isolation structures on the substrate, each isolation structure being formed between adjacent fins;
forming a first opening by etching at least one isolation structure of the plurality of isolation structures and a portion of the substrate; and
forming a power rail by filling the first opening with a conductive material, wherein a top surface of the power rail is lower than a top surface of the plurality of fins,
wherein forming the first opening by etching the at least one isolation structure and the portion of the substrate includes:
etching the at least one isolation structure till a surface of the portion of the substrate is exposed to form a first trench;
continuously etching the portion of the substrate along the first trench to form the first opening; and
etching the at least one isolation structure includes:
forming a patterned photoresist layer on the isolation structure layer;
using the patterned photoresist layer as a mask, etching the at least one isolation structure to form a second trench;
removing the patterned photoresist layer;
forming a first mask layer on the isolation structure layer, and on sidewalls and a bottom of the second trench;
etching the first mask layer to form a second opening and exposing the bottom of the second trench by the second opening; and
etching the at least one isolation structure along the second opening till the surface of the substrate is exposed to form the first trench.

9. The method according to claim 8 , wherein etching the first mask layer includes:
forming a second mask layer on the first mask layer, wherein the second mask layer exposes the first mask layer at the bottom of the second trench; and
using the second mask layer as a mask, removing the first mask layer at the bottom of the second trench to form the second opening.

10. The method according to claim 8 , wherein:
the first mask layer is made of a material including silicon nitride, aluminum nitride, silicon carbide, or a combination thereof.

11. The method according to claim 9 , wherein:
the second mask layer is made of a hydrocarbon polymer.

12. The method according to claim 8 , wherein forming the power rail includes:
forming a conductive material layer by filling the first opening with the conductive material;
performing a chemical mechanical polishing process on the conductive material layer, such that a top of the conductive material layer is coplanar with a surface of the first mask layer; and
forming the power rail by removing a portion of the conductive material layer, such that the top surface of the power rail is lower than the top surface of the plurality of fins.

13. The method according to claim 12 , wherein:
the conductive material layer is etched by a dry etching process having process parameters including:
an etching gas, including carbon tetrafluoride, boron trichloride, oxygen, chlorine, helium, or a combination thereof;
an etching pressure of about 2 mTorr to about 100 mTorr; and
an etching temperature of about 0° C. to about 150° C.

Assignees

• Semiconductor Mfg Int Shanghai Corp
• Semiconductor Mfg Int Beijing Corp

Inventors

• Zhang Haiyang
• Liu Panpan

Classifications

• H10P52/403

  of conductive or resistive materials · CPC title

• H10P50/267 Primary

  using plasmas · CPC title

• H10W20/4462

  Carbon or carbon-containing materials, e.g. graphene · CPC title

• H10W20/4441

  the principal metal being a refractory metal · CPC title

• H10W20/4421

  the principal metal being copper · CPC title