Plurality of transistor packages with exposed source and drain contacts mounted on a carrier

US11600558B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-11600558-B2
Application numberUS-202016845304-A
CountryUS
Kind codeB2
Filing dateApr 10, 2020
Priority dateApr 12, 2019
Publication dateMar 7, 2023
Grant dateMar 7, 2023

How to read this patent

A practical reading order for non-experts. Skip the full description unless you need deep technical detail.

  1. Title

    What the patent document calls the invention.

  2. Abstract

    A short plain-language summary of the technical disclosure.

  3. Assignees and inventors

    Who owns or filed the patent and who is credited as inventor.

  4. Key dates

    Filing, priority, publication, and grant dates set the timeline.

  5. First independent claim

    The legal scope of protection — read this for what is actually claimed.

  6. CPC / IPC classifications

    Technology tags used to group this patent with similar filings.

  7. Citations and related patents

    Prior art links and similar publications in this corpus.

Abstract

Official abstract text for this publication.

A chip package is provided. The chip package includes a semiconductor chip having on a front side a first connecting pad and a second connecting pad, a carrier having a pad contact area and a recess, encapsulation material encapsulating the conductor chip, a first external connection that is free from or extends out of the encapsulation material, an electrically conductive clip, and a contact structure. The semiconductor chip is arranged with its front side facing the carrier with the first connecting pad over the recess and with the second connecting pad contacting the pad contact area. The clip is arranged over a back side of the semiconductor chip covering the semiconductor chip where it extends over the recess. The electrically conductive contact structure electrically conductively connects the first connecting pad with the first external connection.

First claim

Opening claim text (preview).

What is claimed is: 1. A half-bridge module, comprising: a carrier comprising a top side, a first source pad and a first drain pad; a first transistor package comprising a first source contact surface exposed at a bottom side of the first transistor package, and a first drain contact surface exposed at a top side of the first transistor package, wherein the first transistor package is mounted to the top side of the carrier with the first source contact surface electrically and mechanically contacting the first source pad; and a second transistor package comprising a second source contact surface exposed at a top side of the second transistor package, and a second drain contact surface exposed at a bottom side of the second transistor package, wherein the second transistor package is mounted to the top side of the carrier with the second drain contact surface electrically and mechanically contacting the first drain pad, wherein a portion of the first source pad is exposed at the top side at a first end of the carrier, wherein a portion of the first drain pad is exposed at the top side at a second end of the carrier opposite the first end. 2. The half-bridge module of claim 1 , further comprising: at least one fixing structure at the first source pad and/or at the first drain pad, wherein the at least one fixing structure is configured to provide or enable a mechanical fixation and an electrically conductive coupling between the first source pad and a further first source pad of an adjacent further half-bridge module, and/or a mechanical fixation and an electrically conductive coupling between the first drain pad and a further first drain pad of the adjacent further half-bridge module. 3. The half-bridge module of claim 2 , wherein the at last one fixing structure is at least one screw hole formed in the first source pad and/or in the first drain pad. 4. The half-bridge module of claim 2 , wherein the at least one fixing structure is at least one locking element attached to the first source pad and/or to the first drain pad and configured to couple to a corresponding further locking element of the further half-bridge module. 5. The half-bridge module of claim 1 , wherein the first drain contact surface exposed at a top side of the first transistor package and the second source contact surface exposed at a top side of the second transistor package are arranged at a same distance from a top side surface of the carrier. 6. The half-bridge module of claim 5 , wherein the carrier comprises an insulated through hole for fixing a common conductor element to the half-bridge module, and wherein the common conductor element is configured to be in electrically conductive contact with the first drain contact surface and the second source contact surface. 7. The half-bridge module of claim 5 , further comprising: a common conductor element in electrically conductive contact with the first drain contact surface and the second source contact surface. 8. The half-bridge module of claim 7 , further comprising: at least one conductor locking element attached to the common conductor element and configured to couple to a corresponding further conductor locking element of a further adjacent half-bridge module. 9. The half-bridge module of claim 8 , wherein the at least one conductor locking element extends over at least one edge of the carrier that connects the first end and the second end of the carrier. 10. The half-bridge module of claim 8 , wherein the at least one conductor locking element comprises two conductor locking elements extending over both edges of the carrier that connect the first end and the second end. 11. A three-phase system, comprising: at least three half-bridge modules in accordance with claim 1 ; wherein the at least three half-bridge modules are coupled to form the three-phase system. 12. A three-phase system, comprising: at least six half-bridge modules in accordance with claim 1 , wherein a first half-bridge module and a second half-bridge module of the at least six half-bridge modules are coupled in parallel to provide a first phase of the three-phase system, wherein a third half-bridge module and a fourth half-bridge module of the at least six half-bridge modules are coupled in parallel to provide a second phase of the three-phase system, wherein a fifth half-bridge module and a sixth half-bridge module of the at least six half-bridge modules are coupled in parallel to provide a third phase of the three-phase system, wherein the first drain contact surface and the second source contact surface of each of the first half-bridge module and of the second half-bridge module are conductively coupled by a first common conductor element, wherein the first drain contact surface and the second source contact surface of each of the third half-bridge module and of the fourth half-bridge module are conductively coupled by a second common conductor element, wherein the first drain contact surface and the second source contact surface of each of the fifth half-bridge module and of the sixth half-bridge module are conductively coupled by a third common conductor element. 13. The three-phase system of claim 12 , further comprising: a further common conductor element conductively coupled to the first source pad of each of the first half-bridge module, the second half-bridge module, the third half-bridge module and the fourth half-bridge module. 14. The three-phase system of claim 12 , further comprising: a further common conductor element conductively coupled to the first drain pad of each of the third half-bridge module, the fourth half-bridge module the fifth half-bridge module, and the sixth half-bridge module.

Assignees

Inventors

Classifications

  • Encapsulations, e.g. protective coatings · CPC title

  • Multiple chips on leadframes · CPC title

  • Package configurations · CPC title

  • forming a chip-scale package [CSP] · CPC title

  • the semiconductor body being completely enclosed · CPC title

Patent family

Related publications grouped by family.

External sources

Frequently asked questions

Answers are generated from the same data shown on this page.

What does patent US11600558B2 cover?
A chip package is provided. The chip package includes a semiconductor chip having on a front side a first connecting pad and a second connecting pad, a carrier having a pad contact area and a recess, encapsulation material encapsulating the conductor chip, a first external connection that is free from or extends out of the encapsulation material, an electrically conductive clip, and a contact s…
Who is the assignee on this patent?
Infineon Technologies Ag
What technology area does this patent fall under?
Primary CPC classification H10W70/481. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Mar 07 2023 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 3 related publications on this page (citations in our corpus or others sharing the same primary CPC).