Scheduling configuration for deep learning networks

Patent metadata

Field	Value
Publication number	US-11599777-B2
Application number	US-201715499900-A
Country	US
Kind code	B2
Filing date	Apr 28, 2017
Priority date	Apr 28, 2017
Publication date	Mar 7, 2023
Grant date	Mar 7, 2023

Abstract

In an example, an apparatus comprises a plurality of execution units comprising and logic, at least partially including hardware logic, to traverse a solution space, score a plurality of solutions to a scheduling deep learning network execution, and select a preferred solution from the plurality of solutions to implement the deep learning network. Other embodiments are also disclosed and claimed.

First claim

The invention claimed is:

1. An apparatus comprising:
a cluster of interconnected graphics processors, each graphics processor including a plurality of processing resources comprising at least a first type of processing resource and a second type of processing resource, different from the first type of processing resource, the graphics processors of the cluster of interconnected graphics processors interconnected via a first plurality of point-to-point interconnects, at least a portion of the graphics processors of the cluster of interconnected graphics processors additionally interconnected via a second plurality of interconnects to a host interface switch; and
processing circuitry to schedule operations to the cluster of interconnected graphics processors, the processing circuitry configured to:
determine a traversal strategy for a deep learning neural network comprising an input layer and an output layer separated by at least one hidden layer which transforms an input received by the input layer into a representation useful for generating an output in the output layer, the traversal strategy to be implemented via dispatch components of the graphics processors in the cluster of interconnected graphics processors; and
convey the traversal strategy to the dispatch components of the graphics processors, the traversal strategy for a three-dimensional (3D) object divided into 3D tiles, each tile represented as a 3D cube in memory of the graphics processors, the graphics processors configured to:
receive the traversal strategy and data for the deep learning neural network;
traverse a solution space of the deep learning neural network to score a plurality of solutions to schedule deep learning network execution on the plurality of processing resources of a graphics processor;
select a solution from the plurality of solutions to implement the deep learning network based on scores associated with the plurality of solutions; and
implement a workload schedule to assign tasks to the plurality of processing resources, wherein the workload schedule specifies a batch of grouped operations, the operations of the batch of grouped operations determined via a machine learning model based on historical data associated with the cluster of interconnected graphics processors.

2. The apparatus of claim 1 , wherein:
the solution defines a tile size for the deep learning network.

3. The apparatus of claim 1 , wherein:
the solution defines a traversal order for the deep learning network.

4. The apparatus of claim 1 , wherein:
the solution defines a buffering level for the deep learning network.

5. The apparatus of claim 1 , wherein:
the solution defines a data type for the deep learning network.

6. The apparatus of claim 1 , wherein a scheduler component is to determine a traversal strategy for a deep learning neural network execution and forward the traversal strategy to the plurality of processing resources.

7. The apparatus of claim 1 , wherein the plurality of processing resources is on a single integrated circuit.

8. An electronic device, comprising:
a cluster of interconnected graphics processors, each graphics processor including a plurality of processing resources comprising at least a first type of processing resource and a second type of processing resource, different from the first type of processing resource, the graphics processors of the cluster of interconnected graphics processors interconnected via a first plurality of point-to-point interconnects, at least a portion of the graphics processors of the cluster of interconnected graphics processors additionally interconnected via a second plurality of interconnects to a host interface switch; and
a processor, separate from the plurality of processing resources, to schedule operations to the cluster of interconnected graphics processors, the processor configured to:
determine a traversal strategy for a deep learning neural network comprising an input layer and an output layer separated by at least one hidden layer which transforms an input received by the input layer into a representation useful for generating an output in the output layer, the traversal strategy to be implemented via dispatch components of the graphics processors in the cluster of interconnected graphics processors;
convey the traversal strategy to the dispatch components of the graphics processors, the traversal strategy for a three-dimensional (3D) object divided into 3D tiles, each tile represented as a 3D cube in memory of the graphics processors, the graphics processors configured to;
receive the traversal strategy and data for the deep learning neural network;
traverse a solution space of the deep learning neural network to score a plurality of solutions to schedule deep learning network execution on the plurality of processing resources of a graphics processor;
select a solution from the plurality of solutions to implement the deep learning network based on scores associated with the plurality of solutions; and
implement a workload schedule to assign tasks to the plurality of processing resources, wherein the workload schedule specifies a batch of grouped operations, the operations of the batch of grouped operations determined via a machine learning model based on historical data associated with the cluster of interconnected graphics processors.

9. The electronic device of claim 8 , wherein:
the solution defines a tile size for the deep learning network.

10. The electronic device of claim 8 , wherein:
the solution defines a traversal order for the deep learning network.

11. The electronic device of claim 8 , wherein:
the solution defines a buffering level for the deep learning network.

12. The electronic device of claim 8 , wherein:
the solution defines a data type for the deep learning network.

13. The electronic device of claim 8 , wherein a scheduler component is to determine a traversal strategy for a deep learning neural network execution and forward the traversal strategy to the plurality of processing resources.

14. The electronic device of claim 8 , wherein the plurality of processing resources is on a single integrated circuit.

Assignees

• Intel Corp

Inventors

• Ben-Avi Eran
• Zmora Neta
• Jacob Guy
• Faivishevsky Lev
• Dreyfuss Jeremie
• Bar-On Tomer
• Subag Jacob
• Fais Yaniv
• Hirsch Shira
• Weisel Orly
• Walter Zigi
• Oren Yarden

Classifications

• G06N3/0895

  Weakly supervised learning, e.g. semi-supervised or self-supervised learning · CPC title

• G06N3/098

  Distributed learning, e.g. federated learning · CPC title

• G06N3/09

  Supervised learning · CPC title

• G06N3/0442

  characterised by memory or gating, e.g. long short-term memory [LSTM] or gated recurrent units [GRU] · CPC title

• G06N3/0464

  Convolutional networks [CNN, ConvNet] · CPC title