Packet queueing for network device

Patent metadata

Field	Value
Publication number	US-11599490-B1
Application number	US-201815913786-A
Country	US
Kind code	B1
Filing date	Mar 6, 2018
Priority date	Apr 14, 2016
Publication date	Mar 7, 2023
Grant date	Mar 7, 2023

Abstract

A packet header is received from a host and written to a header queue. A direct memory access (DMA) descriptor is received from the host and written to a packet descriptor queue. The DMA descriptor points to packet data in a host memory. The packet data is fetched from host memory and the packet header and the packet data are provided to a network interface.

First claim

What is claimed is:

1. A device, comprising:
a network interface;
a first memory configured to store a packet header of a network packet and a direct memory access (DMA) descriptor of payload data of the network packet stored in a second memory separate from the first memory, the packet header and the payload data being received from a host system; and
processing logic configured to:
perform a first read operation at the first memory to obtain the packet header;
perform, based on executing the DMA descriptor, a second read operation at the second memory to obtain the payload data; and
provide the packet header and the payload data to the network interface to generate the network packet for transmission via the network interface to a network.

2. The device of claim 1 , further comprising a bus interface and a function, wherein:
the function provides access to the network interface;
the bus interface is coupled with the host system via a root complex and is configured to:
receive, from the root complex, the packet header and the payload data; and
provide the packet header and the payload data to the processing logic; and
the processing logic is configured to provide the packet header and the payload data to the function to generate the network packet for transmission.

3. The device of claim 2 , wherein:
the first memory includes a memory portion reserved for memory-mapped input/output (MMIO) write transactions, the memory portion being accessible by the bus interface; and
the bus interface is configured to:
receive a first write transaction to store the packet header;
receive a second write transaction including the payload data; and
store the packet header and the payload data at the memory portion.

4. The device of claim 2 , wherein the bus interface operates based on a bus protocol comprising one of: Peripheral Component Interconnect (PCI), PCI-eXtended (PCI-X), Accelerated Graphics Port (AGP), PCI Express (PCIe), Industry Standard Architecture (ISA), Extended ISA (EISA), Video Electronics Standards Association (VESA), Micro Channel, or Advanced Technology Attachment (ATA).

5. The device of claim 1 , wherein:
the host system includes a guest virtual machine and a hypervisor; and
the packet header and the payload data are received from the hypervisor of the host system.

6. The device of claim 1 , further comprising a register accessible by the host system and by the processing logic, wherein
the register is configured to:
receive, from the host system, an indication that the packet header is stored in the first memory;
store the indication; and
provide the indication to the processing logic to enable the processing logic to obtain the packet header from the first memory.

7. The device of claim 6 , wherein the indication stored in the register comprises at least one of: an interrupt signal, or a location of the packet header in the first memory.

8. The device of claim 1 , wherein:
the processing logic comprises a direct memory access (DMA) engine coupled with the second memory configured to execute the DMA descriptor.

9. The device of claim 8 , wherein the DMA engine is further configured to receive the packet header from the processing logic and provide the packet header and the payload data to the network interface.

10. The device of claim 1 , wherein:
the first memory stores a first queue and a second queue;
the first queue stores a set of packet headers received from the host system; and
the second queue stores a set of DMA descriptors included in previously-received payload information from the host system.

11. The device of claim 10 , wherein:
each of the first queue and the second queue includes a circular queue including a head pointer and a tail pointer; and
the processing logic is configured to obtain the packet header based on the tail pointer of the first queue.

12. The device of claim 10 , wherein the set of packet headers stored in the first queue and the set of DMA descriptors stored in the second queue have a one-to-one correspondence.

13. The device of claim 10 , wherein the processing logic is further configured to:
obtain the packet header from the first memory;
modify the packet header; and
provide the modified packet header to the network interface to generate the network packet including the modified packet header and the payload data.

14. The device of claim 1 , wherein the processing logic is further configured to write to a completion queue in the second memory after the network packet is transmitted by the network interface.

15. The device of claim 1 , wherein the second memory is external to the device.

16. A computer-implemented method comprising:
receiving, from a host system, a packet header of a network packet;
storing the packet header at a first memory;
receiving, from the host system, a direct memory access (DMA) descriptor of payload data of the network packet stored in a second memory of the host system, the second memory being separate from the first memory;
storing the DMA descriptor at the first memory;
performing a first read operation at the first memory to obtain the packet header;
performing, based on executing the DMA descriptor, a second read operation at the second memory to obtain the payload data;
assembling the network packet to include the packet header and the payload data; and
transmitting the network packet to a network.

17. An apparatus comprising:
means for receiving, from a host system, a packet header of a network packet;
means for storing the packet header at a first memory;
means for receiving, from the host system, a direct memory access (DMA) descriptor of payload data of the network packet stored in a second memory of the host system, the second memory being separate from the first memory;
means for storing the DMA descriptor at the first memory;
means for performing a first read operation at the first memory to obtain the packet header;
means for performing, based on executing the DMA descriptor, a second read operation at the second memory to obtain the payload data;
means for assembling the network packet to include the packet header and the payload data; and
means for transmitting the network packet to a network.

18. The device of claim 1 , wherein:
the network packet is a first network packet;
the packet header is a first packet header;
the payload data is first payload data; and
the processing logic is further configured to, based on determining that a number of packet headers stored in the first memory, including the first packet header, exceeds a threshold:
transmit a notification to the host system to enable the host system to store both a second packet header and second payload data of a second network packet at the second memory;
obtain the second packet header and the second payload data from the second memory; and
provide the second packet header and the second payload data to the network interface to generate the second network packet for transmission.

19. The device of claim 1 , wherein:
the network packet is a first network packet;
the packet header is a first packet header;
the payload data is a first payload data; and
the processing logic is further configured to:
receive a second packet header and second payload data of a second network packet from the host system;
store the second packet header and the second payload data in the first memory;

perform read operations at the first memory to obtain the second packet header and the second payload data;

Assignees

• Amazon Tech Inc

Inventors

• Machulsky Georgy
• Bshara Nafea
• Belgazal Netanel Israel
• Schmeilin Evgeny
• Bshara Said

Classifications

• G06F13/28 Primary

  using burst mode transfer, e.g. direct memory access {DMA}, cycle steal (G06F13/32 takes precedence) · CPC title

• G06F13/4068

  Electrical coupling · CPC title

• G06F13/404

  with address mapping · CPC title

• H04L69/321

  Interlayer communication protocols or service data unit [SDU] definitions; Interfaces between layers · CPC title

• G06F13/4282

  on a serial bus, e.g. I2C bus, SPI bus (on daisy chain buses G06F13/4247) · CPC title