Dynamic generation of layout adaptive packaging

US11599032B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-11599032-B2
Application numberUS-201917285741-A
CountryUS
Kind codeB2
Filing dateAug 28, 2019
Priority dateNov 15, 2018
Publication dateMar 7, 2023
Grant dateMar 7, 2023

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

    Technology tags used to group this patent with similar filings.

  7. Citations and related patents

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Abstract

Official abstract text for this publication.

Aspects of disclosure provide a method for attaching wiring connections to a component using both design and field measured data of the component to produce accurate wiring connections.

First claim

Opening claim text (preview).

What is claimed is: 1. A method for processing an apparatus in a maskless lithography system, comprising: obtaining coordinate data on a component and an aspect of an electrical connection to the component in a designed state; placing the component within range of at least one scanning device associated with the lithography system; scanning the component with the at least one scanning device to develop a second set of coordinate data for the component; comparing the obtained coordinate data of the component to the second set of coordinate data for the component to determine an offset of the component scanned with the scanning device to the designed state; altering the aspect of the electrical connection to the component based, at least in part, upon one of the offset data, visual images of the scanning of the component used to develop the second set of coordinate data for the component, and the second set of coordinate data for the component prior to the forming the electrical connection; providing an electrical connection wiring location between the component and a fixed perimeter using the altered aspect of the electrical connection; and forming an altered electrical connection on the electrical connection location between the component and the fixed perimeter, wherein the method is performed in-situ in the maskless lithography system. 2. The method according to claim 1 , wherein the component is placed upon a substrate, and wherein the substrate is placed upon an indexing table of the lithography system. 3. The method according to claim 1 , wherein the altering the aspect of the electrical connection is performed by computer analysis. 4. The method according to claim 1 , wherein the comparing the obtained coordinate data to the second set of coordinate data further comprises comparing the offset to a threshold. 5. The method according to claim 4 , further comprising: when the offset is less than the threshold, setting the offset to zero. 6. The method according to claim 1 , further comprising: comparing the obtained coordinate data to the second set of coordinate data further comprises comparing the offset to a threshold; and when the comparing is greater than the threshold, generating a warning to a user that the threshold has been exceeded. 7. The method according to claim 1 , further comprising: manufacturing the electrical connection based upon data of the aspect of the electrical connection that is altered. 8. The method according to claim 1 , wherein the altering the aspect of the electrical connection is based upon the offset data. 9. The method according to claim 1 , wherein the component is placed upon a substrate. 10. A method for processing an apparatus in a maskless microlithography system, comprising: obtaining position data on a component and an aspect of an electrical connection to the component for a designed state; placing the component on a stage of a microlithography system; placing the stage within range of at least one scanning device of the microlithography system; scanning the stage including the component with the at least one scanning device to develop a second set of coordinate data for the component and the electrical connection; comparing the obtained coordinate data of the component to the second set of coordinate data for the component to determine an offset of the component scanned with the scanning device to the designed state; altering the aspect of the electrical connection to the component based, at least in part, upon the offset data prior to forming the electrical connection; providing an electrical connection wiring location between the component and a fixed perimeter using the altered aspect of the electrical connection; and forming the altered electrical connection on the electrical connection location between the component and the fixed perimeter, wherein the method is performed in-situ in the maskless lithography system. 11. The method according to claim 10 , further comprising: manufacturing the electrical connection based upon data of the aspect of the electrical connection that is altered. 12. The method according to claim 10 , wherein the component is placed upon a substrate. 13. The method according to claim 10 , wherein the altering of the aspect of the electrical connection is performed by computer analysis, or wherein the comparing the obtained coordinate data to the second set of coordinate data further comprises comparing the offset to a threshold. 14. The method according to claim 10 , wherein the microlithography system is a maskless system, or wherein the comparing the obtained coordinate data to the second set of coordinate data further comprises comparing the offset to a threshold. 15. The method according to claim 10 , wherein the aspect of the electrical connection is performed by computer analysis. 16. The method according to claim 10 , wherein the microlithography system is a maskless system. 17. A method for processing a substrate in a maskless microlithography system, comprising: obtaining coordinate data in a designed state pertaining to at least one component and an aspect of at least one wiring connection to the at least one component, wherein the component is at least one of on and in the substrate; placing the substrate on a stage within the microlithography system; moving the substrate on the stage to a scanning device of the lithography system; scanning the substrate including the component with the scanning device to develop a second set of coordinate data for the component; comparing the obtained coordinate data of the component of the stage to the second set of coordinate data for the component to determine an offset of the component scanned with the scanning device to the designed state; altering the aspect of the at least one wiring connection to the component based, at least in part, upon one of the offset data, visual images of the scanning of the component used to develop the second set of coordinate data for the component and the second set of coordinate data for the component prior to forming the electrical connection; providing an electrical connection wiring location between the component and a fixed perimeter using the altered aspect of the electrical connection; and forming the altered electrical connection on the electrical connection location between the component and the fixed perimeter, wherein the method is performed in-situ in the maskless lithography system. 18. The method according to claim 17 , further comprising: manufacturing the at least one wiring connection pattern based upon data of the aspect of the at least one wiring connection pattern. 19. The method according to claim 17 , wherein the altering the aspect of the at least one wiring connection is performed by computer analysis, or wherein the comparing the obtained coordinate data to the second set of coordinate data further comprises comparing the offset to a threshold, or wherein the component is a semiconductor component. 20. The method according to claim 17 , wherein the altering the aspect of the at least one wiring connection is based upon the offset data.

Assignees

Inventors

Classifications

  • Photolithographic processes · CPC title

  • Direct write, i.e. pattern is written directly without the use of a mask by one or multiple beams (maskless lithography using a programmable mask G03F7/70291) · CPC title

  • Addressable masks, e.g. spatial light modulators [SLMs], digital micro-mirror devices [DMDs] or liquid crystal display [LCD] patterning devices · CPC title

  • Data handling in all parts of the microlithographic apparatus, e.g. handling pattern data for addressable masks or data transfer to or from different components within the exposure apparatus · CPC title

  • Exposure without an original mask, e.g. using a programmed deflection of a point source, by scanning, by drawing with a light beam, using an addressed light or corpuscular source (G03F7/70 takes precedence) · CPC title

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Frequently asked questions

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What does patent US11599032B2 cover?
Aspects of disclosure provide a method for attaching wiring connections to a component using both design and field measured data of the component to produce accurate wiring connections.
Who is the assignee on this patent?
Applied Materials Inc
What technology area does this patent fall under?
Primary CPC classification G03F7/70291. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Mar 07 2023 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 5 related publications on this page (citations in our corpus or others sharing the same primary CPC).