Three-dimensional memory device with corrosion-resistant composite spacer

Patent metadata

Field	Value
Publication number	US-11594552-B2
Application number	US-202017100841-A
Country	US
Kind code	B2
Filing date	Nov 21, 2020
Priority date	Jul 24, 2018
Publication date	Feb 28, 2023
Grant date	Feb 28, 2023

Abstract

Embodiments of a three-dimensional (3D) memory device with a corrosion-resistant composite spacer and method for forming the same are disclosed. In an example, a method for forming a 3D memory device is disclosed. A dielectric stack including a plurality of dielectric/sacrificial layer pairs is formed on a substrate. A memory string extending vertically through the dielectric stack is formed. A slit extending vertically through the dielectric stack is formed. A memory stack is formed on the substrate including a plurality of conductor/dielectric layer pairs by replacing, with a plurality of conductor layers, the sacrificial layers in the dielectric/sacrificial layer pairs through the slit. A composite spacer is formed along a sidewall of the slit. The composite spacer includes a first silicon oxide film, a second silicon oxide film, and a dielectric film formed laterally between the first silicon oxide film and the second silicon oxide film. A slit contact extending vertically in the slit is formed.

First claim

What is claimed is:

1. A method for forming a three-dimensional (3D) memory device, comprising:
forming a dielectric stack comprising a plurality of dielectric/sacrificial layer pairs on a substrate;
forming a memory string extending vertically through the dielectric stack;
forming a slit extending vertically through the dielectric stack;
forming a memory stack on the substrate comprising a plurality of conductor/dielectric layer pairs by replacing, with a plurality of conductor layers, the sacrificial layers in the dielectric/sacrificial layer pairs through the slit;
forming a composite spacer along a sidewall of the slit, the composite spacer comprising a first silicon oxide film, a second silicon oxide film, and a dielectric film formed laterally between the first silicon oxide film and the second silicon oxide film, comprising:
forming the first silicon oxide film by filling a first silicon oxide to fully fill remaining lateral recesses of a gate structure that comprises a gate conductor, the first silicon oxide being in contact with the gate conductor in the remaining lateral recesses;
forming the dielectric film without being present in the remaining lateral recesses; and
forming the second silicon oxide film at a temperature higher than a temperature forming the first silicon oxide; and

forming a slit contact extending vertically in the slit.

2. The method of claim 1 , wherein forming the memory stack comprises:
etching the sacrificial layers in the plurality of dielectric/sacrificial layer pairs through the slit; and
depositing the conductor layers in the plurality of conductor/dielectric layer pairs through the slit.

3. The method of claim 2 , further comprising depositing a gate dielectric layer in each conductor/dielectric layer pair prior to depositing the conductor layers.

4. The method of claim 3 , wherein the gate dielectric layer is deposited along the sidewall of the slit.

5. The method of claim 3 , wherein a portion of the first silicon oxide film is in contact with the gate dielectric layer.

6. The method of claim 2 , wherein the deposition of the conductor layers uses a precursor containing fluorine.

7. The method of claim 6 , wherein the conductor layers comprise tungsten, and the precursor comprises tungsten hexafluoride.

8. The method of claim 1 , wherein forming the composite spacer comprises:
forming the first silicon oxide film along the sidewall of the slit;
forming the dielectric film along the first silicon oxide film; and
forming the second silicon oxide film along the dielectric film.

9. The method of claim 1 , wherein a first temperature for forming the first silicon oxide is not higher than 400° C., and a second temperature for forming the second silicon oxide film is not lower than 400° C.

10. The method of claim 1 , wherein the dielectric film comprises a high dielectric constant (high-k) dielectric material.

11. The method of claim 10 , wherein the high-k dielectric material comprises aluminum oxide.

12. The method of claim 1 , wherein a thickness of the dielectric film is between about 1 nm and about 10 nm.

13. The method of claim 12 , wherein the thickness of the dielectric film is between about 3 nm and about 7 nm.

14. The method of claim 1 , wherein the dielectric film comprises a plurality of dielectric sub-films stacked laterally.

15. The method of claim 14 , wherein the plurality of dielectric sub-films comprise a plurality of dielectric materials.

16. The method of claim 14 , wherein each dielectric sub-film comprises different dielectric materials.

17. The method of claim 14 , where a portion of the dielectric sub-films comprises a same dielectric material.

18. The method of claim 1 , wherein the slit extends laterally to separate the memory stack into a plurality of blocks.

19. The method of claim 1 , wherein a first temperature for forming the first silicon oxide is not higher than 600° C., and a second temperature for forming the second silicon oxide film is not lower than 600° C.

20. A method for forming a three-dimensional (3D) memory device, comprising:
forming a dielectric stack comprising a plurality of dielectric/sacrificial layer pairs on a substrate;
forming a memory string extending vertically through the dielectric stack;
forming a slit extending vertically through the dielectric stack;
forming a memory stack on the substrate comprising a plurality of conductor/dielectric layer pairs by replacing, with a plurality of conductor layers, the sacrificial layers in the dielectric/sacrificial layer pairs through the slit;
forming a composite spacer along a sidewall of the slit, the composite spacer comprising a first silicon oxide film, a second silicon oxide film, and a dielectric film formed laterally between the first silicon oxide film and the second silicon oxide film, comprising:
forming the first silicon oxide film by filling a first silicon oxide into remaining lateral recesses of a gate structure, the remaining lateral recesses being fully filled by the first silicon oxide; and
forming the dielectric film without being present in the remaining lateral recesses, the dielectric film comprising a plurality of high-k dielectric sub-films stacked laterally; and forming a slit contact extending vertically in the slit.

Assignees

• Yangtze Memory Tech Co Ltd

Inventors

• Xu Bo
• Yan Ping
• Yang Chuan
• Gao Jing
• Huo Zongliang
• Zhang Lu

Classifications

• H10P14/6339

  deposition by cyclic CVD, e.g. ALD, ALE or pulsed CVD · CPC title

• H10P14/6334

  using decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition (deposition by physical ablation of a target H10P14/6329) · CPC title

• H10P14/6322

  Formation by thermal treatments (formation by plasma treatment H10P14/6319) · CPC title

• H10P14/6308

  of Group IV semiconductors · CPC title

• H10P14/69391

  the material containing aluminium, e.g. Al2O3 · CPC title