Chopper stabilized analog multiplier unit element with binary weighted charge transfer capacitors

Patent metadata

Field	Value
Publication number	US-11593573-B2
Application number	US-202117334890-A
Country	US
Kind code	B2
Filing date	May 31, 2021
Priority date	May 31, 2021
Publication date	Feb 28, 2023
Grant date	Feb 28, 2023

Abstract

A Unit Element (UE) has a positive UE and a negative UE, each having a digital X input and a digital W input with a sign bit, the sign bit is exclusive ORed with a chop clock to generate a chopped sign bit. The positive UE is enabled when the chopped sign bit is positive and the negative UE is enabled when the chopped sign bit is negative. Each positive and negative UE comprises groups of NAND gates generating an output and complementary output which are coupled to a differential charge transfer bus comprising a positive charge transfer line and a negative charge transfer line. The NAND gate outputs and complementary outputs are coupled through binary weighted charge transfer capacitors the positive charge transfer line and negative charge transfer line.

First claim

We claim:

1. A Chopper Stabilized Multiplier-Accumulator (MAC) Unit Element (UE) performing a bitwise multiplication of an X digital input with a sign bit input and a W digital input and coupling a resultant charge to a charge transfer bus comprising a positive charge transfer line and a negative charge transfer line, the MAC UE comprising:
a chop clock;
a plurality of NAND-groups, each NAND-group receiving one of the W digital input bits, each NAND-group comprising a plurality of NAND gates, each NAND gate of a NAND-group having an input coupled to a W digital input bit, an input coupled to a unique one of the X digital input bits, and a chopped sign bit configured from an exclusive OR (XOR) of the sign bit with the chop clock;
each NAND gate having a positive output and a negative output, the positive output coupled through a binary weighted charge transfer capacitor to a positive charge transfer line, the negative output coupled through a binary weighted charge transfer capacitor to a negative charge transfer line;
each charge transfer capacitor having an associated binary weight, the binary weight for each charge transfer line determined by a sum of bit positions for a corresponding X digital input bit and W digital input bit.

2. The MAC UE of claim 1 where the binary weight is 2 to a power of a sum of the bit positions for a corresponding X digital input bit and a corresponding W digital input bit of a corresponding NAND gate.

3. The MAC UE of claim 1 where each NAND gate generates an output coupled through a binary weighted charge transfer capacitor to the positive charge transfer line and a complement output coupled through a binary weighted charge transfer capacitor to the negative charge transfer line.

4. The MAC UE of claim 1 where the X digital input comprises three bits and the W digital input comprises three bits exclusive of the sign bit.

5. The MAC UE of claim 1 where each NAND gate has a negative output coupled through a binary weighted charge transfer capacitor to the negative charge transfer line and a positive output coupled through a binary weighted charge transfer capacitor to the positive charge transfer line.

6. The MAC UE of claim 1 where each NAND gate has a negative output coupled through a binary weighted charge transfer capacitor to the positive charge transfer line and a positive output coupled through a binary weighted charge transfer capacitor to the negative charge transfer line.

7. The MAC UE of claim 1 where the positive charge transfer capacitor and the negative charge transfer capacitor of a MAC UE with three X bits and three W bits comprise nine charge transfer capacitors, each charge transfer capacitor having a weight of 1 , 2 , 4 , 2 , 4 , 8 , 4 , 8 , and 16 .

8. The MAC UE of claim 1 where the W input chopped sign bit enables or disables the NAND-groups of a MAC UE.

9. The MAC UE of claim 8 where the MAC UE comprises a positive MAC UE which is only enabled when the chopped sign bit is positive and a negative MAC UE which is only enabled with the chopped sign bit is negative.

10. A Multiplier-Accumulator (MAC) unit element (UE) accepting an X digital input and a W digital input accompanied by a sign bit input and a chop clock exclusive ORed with the sign bit and generating a chopped sign bit, the MAC UE comprising:
a charge transfer bus comprising a positive charge transfer line and a negative charge transfer line;
a positive unit element and a negative unit element;
when the chopped sign bit input is positive, the positive unit element operative to perform a bit-by-bit NAND operation asserting an output and also a complement output, the output transferring a charge through a binary weighted charge transfer capacitor to the negative charge transfer line, the complement output transferring a charge through a binary weighted charge transfer capacitor to the positive charge transfer line;
when the chopped sign bit input is negative, the negative unit element operative to perform a bit-by-bit NAND operation asserting an output and also a complement output, the output transferring a charge through a binary weighted charge transfer capacitor to the positive charge transfer line, the complement output transferring a charge through a binary weighted charge transfer capacitor to the negative charge transfer line.

11. The MAC UE of claim 10 where the bit-by-bit NAND operation is performed by a NAND-group, each NAND gate of the NAND-group receiving one of the W input bits, the chopped sign bit, and one of the X input bits to generate a respective output and complement output.

12. The MAC UE of claim 10 where the charge transfer capacitors comprises nine positive charge transfer capacitors and nine negative charge transfer capacitors.

13. The MAC UE of claim 12 where the positive charge transfer capacitors and negative charge transfer capacitors each have weights 1 , 2 , 4 , 2 , 4 , 8 , 4 , 8 , and 16 .

14. The MAC UE of claim 10 where the MAC UE receives a clear input causing all of the NAND outputs to be high and all of the complement outputs to be low.

15. A multiply-accumulate (MAC) unit element (UE) for coupling a multiplication result from an X digital input, a sign bit, a chop clock exclusive ORed with the sign bit to generate a chopped sign bit, and a W digital input as bitwise charge values to a differential charge transfer bus comprising a positive charge transfer line and a negative charge transfer line;
the MAC UE comprising a positive MAC UE which is operative when the chopped sign bit is positive and a negative MAC UE which is operative when the chopped sign bit is negative;
the positive MAC UE comprising a plurality of NAND-groups, one NAND-group for each W digital input bit, each NAND group comprising a plurality of NAND gates, one NAND gate for each X digital input bit, each NAND gate of the NAND-group having an input coupled to one of the W digital input bits, an input coupled to a unique X digital input bit, each NAND gate generating a positive output coupled through a binary weighted charge transfer capacitor to the negative charge transfer line and a negative output coupled through a binary weighted charge transfer capacitor to the positive charge transfer line;
the negative MAC UE comprising a plurality of NAND-groups, one NAND-group for each W digital input bit, each NAND group comprising a plurality of NAND gates, one NAND gate for each X digital input bit, each NAND gate of the NAND-group having an input coupled to one of the W digital input bits, an input coupled to a unique X digital input bit, each NAND gate generating a positive output coupled through a binary weighted charge transfer capacitor to the positive charge transfer line and a negative output coupled through a binary weighted charge transfer capacitor to the negative charge transfer line.

16. The MAC UE of claim 15 where the plurality of positive charge transfer capacitors and the plurality of negative charge transfer capacitors each have relative weights 1 , 2 , 4 , 2 , 4 , 8 , 4 , 8 , and 16 .

17. The MAC UE of claim 15 where each NAND group includes a clear input which initializes a charge on associated binary weighted charge transfer capacitors.

18. The MAC UE of claim 17 where the clear input causes the positive MAC UE and negative MAC UE to assert a positive output high and negative output low.

19. The MAC UE of claim 15 where the X digital input comprises three bits and the W digital input comprises three bits.

Assignees

• Redpine Signals Inc
• Ceremorphic Inc

Inventors

• Kraemer Martin
• Boesch Ryan
• Xiong Wei

Classifications

• H03M1/466

  using switched capacitors · CPC title

• H03M1/38

  sequentially only, e.g. successive approximation type (converting more than one bit per step H03M1/14) · CPC title

• G06J1/00 Primary

  Hybrid computing arrangements · CPC title

• H03K19/20

  characterised by logic function, e.g. AND, OR, NOR, NOT circuits (H03K19/003 - H03K19/01 take precedence) · CPC title

• G06N3/0495

  Quantised networks; Sparse networks; Compressed networks · CPC title