Operating system assisted prioritized thread execution

Patent metadata

Field	Value
Publication number	US-11593154-B2
Application number	US-201816228136-A
Country	US
Kind code	B2
Filing date	Dec 20, 2018
Priority date	Dec 20, 2018
Publication date	Feb 28, 2023
Grant date	Feb 28, 2023

Abstract

The present disclosure is directed to dynamically prioritizing, selecting or ordering a plurality threads for execution by processor circuitry based on a quality of service and/or class of service value/indicia assigned to the thread by an operating system executed by the processor circuitry. As threads are executed by processor circuitry, the operating system dynamically updates/associates respective class of service data with each of the plurality of threads. The current quality of service/class of service data assigned to the thread by the operating system is stored in a manufacturer specific register (MSR) associated with the respective thread. Selection circuitry polls the MSRs on a periodic, aperiodic, intermittent, continuous, or event-driven basis and determines an execution sequence based on the current class of service value associated with each of the plurality of threads.

First claim

What is claimed:

1. A system, comprising:
processor circuitry to execute an operating system, the processor circuitry including a plurality of processor core circuits, each of the processor core circuits to execute a respective one of a plurality of threads;
memory including a plurality of model specific registers (MSRs), each of the plurality of MSRs associated with a respective one of the plurality of threads and to receive MSR data comprising quality of service (QoS) prioritization data from the operating system;
a selection circuitry coupled to the memory, the selection circuitry to:
poll at least one of the plurality of MSRs to obtain the MSR data stored in the associated MSR on an event-driven basis, the event-driven basis comprising a notification of an instantiation of a new thread of the plurality of threads; and
dynamically arrange a thread execution sequence to select one or more requests by at least some of the plurality of threads for execution by the processor circuitry based at least in part on the MSR data associated with the at least some of the plurality of threads and the MSR data associated with each respective one of at least a portion of remaining ones of the plurality of threads and send the thread execution sequence to a scheduling circuitry; and

the scheduling circuitry coupled to the selection circuitry, the scheduling circuitry to receive the thread execution sequence and dynamically schedule execution of the at least some of the plurality of threads by the processor circuitry.

2. The system of claim 1 wherein the QoS prioritization data comprises at least data indicative of one of: a low QoS prioritization level, a medium QoS prioritization level, a high QoS prioritization level, or a multimedia QoS prioritization level.

3. The system of claim 1 wherein the MSR data comprises hardware controlled performance (HWP) data.

4. The system of claim 1 wherein, at intervals, the operating system is to update the MSR data associated with at least a portion of the plurality of threads.

5. The system of claim 1 wherein the selection circuitry is to poll the MSR data at regular intervals.

6. The system of claim 5 wherein the selection circuitry is to reprioritize the thread execution sequence at the regular intervals.

7. The system of claim 1 wherein the event-driven basis includes termination of one of the plurality of threads.

8. A method, comprising:
polling, by selection circuitry, at least some of a plurality of model specific registers (MSRs) to obtain MSR data comprising thread execution prioritization data on an event-driven basis, each of the plurality of MSRs associated with a respective one of a plurality of threads executed by processor circuitry and the event-driven basis comprising a notification of an instantiation of a new thread of the plurality of threads;
dynamically arranging a thread execution sequence, by the selection circuitry, to select one or more requests by at least some of the plurality of threads for execution based at least in part on the MSR data associated with the at least some of the plurality of threads and the MSR data associated with at least a portion of remaining ones of the plurality of threads and send the thread execution sequence to a scheduling circuitry; and
receiving, by the scheduling circuitry, the thread execution sequence and dynamically scheduling execution of the at least some of the plurality of threads by the processor circuitry.

9. The method of claim 8 , further comprising:
dynamically updating, by an operating system executed by the processor circuitry, the MSR data on a periodic basis.

10. The method of claim 9 further comprising:
polling, by the selection circuitry, the at least some of the plurality of MSRs on the periodic basis to obtain the MSR data.

11. The method of claim 8 , further comprising:
dynamically updating, by an operating system executed by the processor circuitry, the MSR data associated with the at least some of the plurality of threads on the event-driven basis.

12. The method of claim 11 further comprising dynamically updating the MSR data on the event-driven basis that includes termination of one of the plurality of threads.

13. The method of claim 8 wherein polling the at least some of the plurality of MSRs to obtain the MSR data comprises:
polling, by the selection circuitry, the at least some of the plurality of MSRs to obtain the MSR data that includes quality of service (QoS) prioritization data associated with each respective one of the plurality of threads.

14. The method of claim 13 wherein polling the at least some of the plurality of MSRs to obtain the MSR data comprising the QoS prioritization data including data indicative of one of: a low QoS prioritization level, a medium QoS prioritization level, a high QoS prioritization level, or a multimedia QoS prioritization level.

15. The method of claim 8 wherein polling the at least some of the plurality of MSRs to obtain the MSR data comprises obtaining:
hardware controlled performance (HWP) data associated with each respective one of the plurality of threads.

16. A system, comprising:
means for polling at least some of a plurality of model specific registers (MSRs) to obtain MSR data comprising thread execution prioritization data on an event-driven basis, each of the plurality of MSRs associated with a respective one of a plurality of threads executed by processor circuitry and the event-driven basis comprising a notification of an instantiation of a new thread of the plurality of threads from the processor circuitry;
means for dynamically arranging a thread execution sequence to select one or more requests by at least some of the plurality of threads for execution based at least in part on the MSR data associated with the respective one of the plurality of threads and the MSR data associated with at least a portion of remaining ones of the plurality of threads and sending the thread execution sequence to a means for scheduling; and
the means for scheduling coupled to the means for dynamically arranging, the means for scheduling to receive the thread execution sequence and dynamically schedule execution of the at least some of the plurality of threads by the processor circuitry.

17. The system of claim 16 , further comprising:
means for dynamically updating the MSR data associated with each of the plurality of threads on a periodic basis.

18. The system of claim 17 wherein the means for polling is for polling the at least some of the plurality of MSRs on the periodic basis to obtain the MSR data.

19. The system of claim 16 , further comprising:
means for dynamically updating the MSR data associated with each of the plurality of threads on an event driven basis.

20. The system of claim 19 wherein the means for dynamically updating the MSR data associated with each of the plurality of threads on an event driven basis comprises:
means for dynamically updating the MSR data associated with each of the plurality of threads on an event driven basis that includes at least one of: the instantiation of the new thread or termination one of the plurality of threads.

21. The system of claim 16 wherein the means for polling is for obtaining the MSR data that includes quality of service (QoS) prioritization data associated with each respective one of the plurality of threads.

22. The system of claim 21 wherein the means for polling is for obtaining the QoS prioritization data including data indicativ

Assignees

• Intel Corp

Inventors

• Samih Ahmad
• Chabukswar Rajshree
• Fenger Russell
• Khasawneh Shadi
• Dhanraj Vijay
• Abozaed Muhammad
• Ramakrishna Mukund
• Kuwahara Atsuo
• Settuvalli Guruprasad
• Gorbatov Eugene
• GUPTA Monica
• Lin Christine M

Classifications

• G06F9/3851 Primary

  from multiple instruction streams, e.g. multistreaming · CPC title

• G06F9/4831 Primary

  with variable priority · CPC title

• G06F2209/5021

  Priority · CPC title

• G06F9/30101

  Special purpose registers · CPC title

• G06F9/5011

  the resources being hardware resources other than CPUs, Servers and Terminals · CPC title