Directed interrupt virtualization with interrupt table

Patent metadata

Field	Value
Publication number	US-11593153-B2
Application number	US-202117643910-A
Country	US
Kind code	B2
Filing date	Dec 13, 2021
Priority date	Feb 14, 2019
Publication date	Feb 28, 2023
Grant date	Feb 28, 2023

Abstract

An interrupt signal is provided to an operating system executed using one or more processors of a plurality of processors. A bus attachment device receives an interrupt signal with an interrupt target ID identifying a processor assigned for use as a target processor for handling the interrupt signal. The bus attachment device translates the received interrupt target ID to a processor ID using an interrupt table entry and forwards the interrupt signal to the target processor for handling. The processor ID is used to address the target processor directly.

First claim

What is claimed is:

1. A computer program product for providing an interrupt signal, the computer program product comprising:
at least one computer readable storage medium readable by at least one processing circuit and storing instructions for performing a method comprising:
receiving an interrupt signal with an interrupt target ID, the interrupt target ID identifying one processor of a plurality of processors of a computing environment assigned for usage as a target processor for handling the interrupt signal;
translating the interrupt target ID to a processor ID; and
forwarding the interrupt signal to the target processor to handle, the forwarding using the processor ID resulting from the translating to address the target processor directly.

2. The computer program product of claim 1 , wherein the interrupt signal being received is in a form of a message signaled interrupt comprising the interrupt target ID of the target processor.

3. The computer program product of claim 1 , wherein the method further comprises retrieving a copy of an interrupt table entry assigned to the interrupt target ID, the copy of the interrupt table entry comprising a first mapping of the interrupt target ID to a processor ID, and wherein the translating uses the copy of the interrupt table entry.

4. The computer program product of claim 1 , wherein the method further comprises:
checking using a copy of a running indicator that the target processor is scheduled for usage by an operating system, the running indicator to indicate whether the target processor identified by the interrupt target ID is scheduled for usage by the operating system; and
continuing, based on the target processor being scheduled, with the forwarding of the interrupt signal.

5. The computer program product of claim 4 , wherein the method further comprises forwarding the interrupt signal for handling to the plurality of processors using broadcasting, based on the target processor not being scheduled.

6. The computer program product of claim 1 , wherein the method further comprises:
checking using an interrupt blocking indicator that the target processor is unblocked enabling receipt of interrupt signals, the interrupt blocking indicator to indicate whether the target processor identified by the interrupt target ID is currently blocked from receiving interrupt signals; and
continuing, based on the target processor being unblocked, with the forwarding of the interrupt signal.

7. The computer program product of claim 6 , wherein the method further comprises forwarding the interrupt signal for handling to remaining processors of the plurality of processors using broadcasting.

8. The computer program product of claim 6 , wherein the method further comprises:
checking that no interrupts addressed to the target processor are pending for handling by the target processor; and
changing based on no interrupts addressed to the target processor being pending for handling by the target processor, the interrupt blocking indicator to indicate the target processor is unblocked.

9. The computer program product of claim 8 , wherein the method further comprises changing, based on the target processor being unblocked, the interrupt blocking indicator in a first copy of an interrupt table entry assigned to the interrupt target ID to indicate the processor ID is blocked, the changing being performed before the forwarding of the interrupt signal to the target processor for handling.

10. The computer program product of claim 9 , wherein the method further comprises:
retrieving based on the changing of the interrupt blocking indicator, a second copy of the interrupt table entry assigned to the interrupt target ID; and
checking the second copy of the interrupt table entry to exclude a predefined type of change of the second copy of the interrupt table entry relative to the first copy of the interrupt table entry, the forwarding of the interrupt signal to the target processor for handling being based on a successful exclusion of the predefined type of change.

11. The computer program product of claim 10 , wherein the predefined type of change is a change of a first mapping of the interrupt target ID relative to a second mapping of the interrupt target ID to another processor ID comprised by the second copy of the interrupt table entry, and based on the second mapping comprising a change relative to the first mapping, the interrupt signal being forwarded for handling to the plurality of processors using broadcasting.

12. The computer program product of claim 10 , wherein the predefined type of change is a change of a first copy of a running indicator indicating that the target processor identified by the interrupt target ID is scheduled for usage by an operating system relative to a second copy of the running indicator, and based on the second copy of the running indicator comprising a change relative to the first copy of the running indicator, the second copy of the running indicator indicating the target processor not being scheduled for usage by an operating system, the interrupt signal being forwarded for handling to the plurality of processors using broadcasting.

13. A computer system for providing an interrupt signal, the computer system comprising:
a memory; and
at least one processor in communication with the memory, wherein the computer system is configured to perform a method, said method comprising:
receiving an interrupt signal with an interrupt target ID, the interrupt target ID identifying one processor of a plurality of processors of a computing environment assigned for usage as a target processor for handling the interrupt signal;
translating the interrupt target ID to a processor ID; and
forwarding the interrupt signal to the target processor to handle, the forwarding using the processor ID resulting from the translating to address the target processor directly.

14. The computer system of claim 13 , wherein the method further comprises retrieving a copy of an interrupt table entry assigned to the interrupt target ID, the copy of the interrupt table entry comprising a first mapping of the interrupt target ID to a processor ID, and wherein the translating uses the copy of the interrupt table entry.

15. The computer system of claim 13 , wherein the method further comprises:
checking using a copy of a running indicator that the target processor is scheduled for usage by an operating system, the running indicator to indicate whether the target processor identified by the interrupt target ID is scheduled for usage by the operating system; and
continuing, based on the target processor being scheduled, with the forwarding of the interrupt signal.

16. The computer system of claim 15 , wherein the method further comprises forwarding the interrupt signal for handling to the plurality of processors using broadcasting, based on the target processor not being scheduled.

17. The computer system of claim 13 , wherein the method further comprises:
checking using an interrupt blocking indicator that the target processor is unblocked enabling receipt of interrupt signals, the interrupt blocking indicator to indicate whether the target processor identified by the interrupt target ID is currently blocked from receiving interrupt signals; and
continuing, based on the target processor being unblocked, with the forwarding of the interrupt signal.

18. The computer system of claim 17 , wherein the method further comprises forwarding the interrupt signal for handling to remaining processors of the plurality of processors us

Assignees

• IBM

Inventors

• Kraemer Marco
• Raisch Christoph
• Schmidt Donald William
• Nerz Bernd
• Lehnert Frank Siegfried
• Driever Peter Dana

Classifications

• G06F9/4881

  Scheduling strategies for dispatcher, e.g. round robin, multi-level priority queues · CPC title

• G06F9/4812 Primary

  by interrupt, e.g. masked · CPC title

• G06F9/45533 Primary

  Hypervisors; Virtual machine monitors · CPC title

• G06F9/45545

  Guest-host, i.e. hypervisor is an application program itself, e.g. VirtualBox · CPC title

• G06F13/24

  using interrupt (G06F13/32 takes precedence) · CPC title