System and method for responsive process security classification and optimization

Patent metadata

Field	Value
Publication number	US-11593079-B2
Application number	US-202117194501-A
Country	US
Kind code	B2
Filing date	Mar 8, 2021
Priority date	Mar 8, 2021
Publication date	Feb 28, 2023
Grant date	Feb 28, 2023

Abstract

A system and method for the storage within one or more virtual execution context registers private code representative of processes or other information requiring an enhanced degree of security. The storage of the private code can be performed as a function of the type of code or in response to one or more markers embedded within the code. The time-variant nature of the virtual execution context registers affords a high degree of inherent security for the private code data stored within.

First claim

The invention claimed is:

1. A system for defining and accessing registers comprising:
at least one virtual execution context memory; and
at least one compiler adapted to:
recognize at least one portion of an executable context defining a private instruction code to be utilized in the execution of at least one particular process upon at least one processor; and
responsively store information representative of the recognized at least one portion of an executable context defining a private instruction code at a specific addressable portion of the at least one virtual execution context memory;
retrieve the information stored at the specific addressable portion of the at least one virtual execution register context memory; and
provide the retrieved information to at least one processor in a format enabling the execution of a process upon the at least one processor, wherein the process is defined, at least in part, by the retrieved information.

2. The system of claim 1 wherein the recognition of the at least one portion of an executable context defining a private instruction code is performed in accordance with a predetermined algorithm.

3. The system of claim 1 wherein the recognition of the at least one portion of an executable context defining a private instruction code is performed in response to a marker associated with the at least one portion of an executable context.

4. The system of claim 1 wherein the at least one processor comprises at least one of the following:
a physical processor; and
a virtual processor.

5. The system of claim 1 wherein the compiler comprises a virtual compiler.

6. The system of claim 1 wherein the virtual execution context memory comprises at least one of the following:
static random-access memory;
dynamic random-access memory;
a non-volatile memory; and
a three-dimensional cross-point memory.

7. The system of claim 1 wherein the recognized at least one portion of an executable context defining a private instruction code comprises at least one of the following:
an encryption key; and
program steps.

8. The system of claim 1 wherein the information representative of the recognized at least one portion of an executable context defining a private instruction code at a specific addressable portion of the at least one virtual execution context memory is stored in accordance with static single assignment protocol.

9. The system of claim 1 wherein the specific addressable portion of the at least one virtual execution context memory comprises at least one register.

10. The system of claim 9 wherein the at least one register comprises at least one of the following:
a register of fixed size; and
a register of variable size.

11. The system of claim 10 wherein the register size comprises a specific register bit width.

12. In a system comprising:
at least one processor; and
at least one virtual execution context memory,
a method for defining and accessing registers comprising the steps of to:
recognizing at least one portion of an executable context defining a private instruction code to be utilized in the execution of at least one particular process upon at least one processor; and
storing, in response to the recognition, information representative of the recognized at least one portion of an executable context defining a private instruction code at a specific addressable portion of the at least one virtual execution context memory;
retrieving the information stored at the specific addressable portion of the at least one virtual execution register context memory; and
providing the retrieved information to the at least one processor in a format enabling the execution of a process upon the at least one processor, wherein the process is defined, at least in part, by the retrieved information.

13. The method of claim 12 wherein recognizing the at least one portion of an executable context defining a private instruction code is performed in accordance with a predetermined algorithm.

14. The method of claim 12 wherein recognizing the at least one portion of an executable context defining a private instruction code is performed in response to a marker associated with the at least one portion of an executable context.

15. The method of claim 12 wherein the at least one processor comprises at least one of the following:
a physical processor; and
a virtual processor.

16. The method of claim 12 wherein the virtual execution context memory comprises at least one of the following:
static random-access memory;
dynamic random-access memory;
a non-volatile memory; and
a three-dimensional cross-point memory.

17. The method of claim 12 wherein the recognized at least one portion of an executable context defining a private instruction code comprises at least one of the following:
an encryption key; and
program steps.

18. The method of claim 12 wherein the step of storing comprises storing information in accordance with static single assignment protocol.

19. The method of claim 12 wherein the specific addressable portion of the at least one virtual execution context memory comprises at least one register.

20. The method of claim 19 wherein the at least one register comprises at least one of the following:
a register of fixed size; and
a register of variable size.

21. The method of claim 20 wherein the register size comprises a specific register bit width.

Assignees

• Beale Andrew Ward
• Strong David
• Unisys Corp

Inventors

• Beale Andrew Ward
• Strong David

Classifications

• G06F8/441 Primary

  Register allocation; Assignment of physical memory space to logical memory space · CPC title