Integrated circuits and manufacturing methods thereof

Patent metadata

Field	Value
Publication number	US-11581314-B2
Application number	US-201916723939-A
Country	US
Kind code	B2
Filing date	Dec 20, 2019
Priority date	May 26, 2010
Publication date	Feb 14, 2023
Grant date	Feb 14, 2023

Abstract

An integrated circuit includes a first diffusion area for a first type transistor. The first type transistor includes a first drain region and a first source region. A second diffusion area for a second type transistor is separated from the first diffusion area. The second type transistor includes a second drain region and a second source region. A gate electrode continuously extends across the first diffusion area and the second diffusion area in a routing direction. A first metallic structure is electrically coupled with the first source region. A second metallic structure is electrically coupled with the second drain region. A third metallic structure is disposed over and electrically coupled with the first and second metallic structures. A width of the first metallic structure is substantially equal to or larger than a width of the third metallic structure.

First claim

What is claimed is:

1. An integrated circuit comprising:
a first diffusion area for a first type transistor, the first type transistor including a first drain region and a first source region in the first diffusion area on a substrate having a top surface;
a second diffusion area for a second type transistor, the second type transistor including a second drain region and a second source region in the second diffusion area;
an isolation structure interposing the first and second diffusion areas;
a gate electrode continuously extending across the first diffusion area and the second diffusion area in a routing direction, wherein the gate electrode has a width extending from a first sidewall to a second sidewall in a width direction, the width direction perpendicular to the routing direction;
an etch stop layer extending over the gate electrode, wherein the etch stop layer is comprised of a first material;
a first metallic structure extending in the routing direction, the first metallic structure overlaps the first diffusion area in the routing direction for a first distance (D1), and wherein the first metallic structure is disposed on a first side of the gate electrode, wherein the first metallic structure is coplanar with the etch stop layer;
a second metallic structure extending in the routing direction, disposed collinear with the first metallic structure, and disposed on the first side of the gate electrode, wherein the second metallic structure overlaps the second diffusion area in the routing direction for a third distance (D3), wherein the second metallic structure is coplanar with the etch stop layer;
a third metallic structure extending in the routing direction, disposed on a second side of the gate electrode, and extending a second distance (D2) over the first diffusion area, extending over the isolation structure, and extending a fourth distance (D4) over the second diffusion area;
wherein the width of the gate electrode interposes the first side and the second side of the gate electrode, wherein the first and second metallic structures are coupled to the first and second source regions and the third metallic structure is coupled to the first and second drain regions;
wherein the etch stop layer directly interfaces a top surface of the gate electrode, directly interfaces a top of a spacer adjacent the gate electrode, and directly interfaces a sidewall of the first metallic structure, wherein the spacer comprises a second material different than the first material and wherein a top surface of the etch stop layer is coplanar with a top surface of the first metallic structure.

2. The integrated circuit of claim 1 , wherein D1 plus D2 is substantially equal to a first width of the first diffusion area in the routing direction.

3. The integrated circuit of claim 2 , wherein D3 plus D4 is substantially equal to a second width of the second diffusion area in the routing direction.

4. The integrated circuit of claim 1 , wherein D1 is greater than D2 and D3 is greater than D4.

5. The integrated circuit of claim 1 , further comprising:
a fourth metallic structure under the first metallic structure and directly interfacing the first source region;
a fifth metallic structure under the second metallic structure and directly interfacing the second source region.

6. The integrated circuit of claim 5 , wherein a width of the fourth metallic structure in a direction perpendicular the routing direction is equal to a width of the first metallic structure in the direction.

7. The integrated circuit of claim 6 , wherein a width of the fifth metallic structure in the direction perpendicular the routing direction is equal to a width of the second metallic structure in the direction.

8. The integrated circuit of claim 5 , wherein the fourth metallic structure is a different composition than the first metallic structure and the fifth metallic structure is a different composition that the second metallic structure.

9. An integrated circuit comprising:
a first diffusion area for a first type transistor, the first type transistor including a first drain region and a first source region in the first diffusion area on a substrate having a top surface;
a second diffusion area for a second type transistor, the second type transistor including a second drain region and a second source region in the second diffusion area;
an isolation structure interposing the first and second diffusion areas;
a gate electrode continuously extending across the first diffusion area and the second diffusion area in a routing direction;
a first copper structure extending in the routing direction from a first end to a second end, the first copper structure overlaps the first diffusion area in the routing direction for a first distance (D1), wherein D1 is measured from the first end;
a second copper structure extending in the routing direction from a third end to a fourth end, and the second copper structure being disposed collinear with the first copper structure, wherein the second copper structure overlaps the second diffusion area in the routing direction for a third distance (D3), wherein D3 is measured from the third end;
a third copper structure extending in the routing direction from a fifth end to a sixth end and having a first portion extending a second distance (D2) over the first diffusion area and a third portion extending a fourth distance (D4) over the second diffusion area, wherein a second portion of the third copper structure extends between the first and third portions, the second portion interfaces a top surface of the isolation structure;
a first tungsten structure below the first portion of the third copper structure and interfacing the first drain region;
a second tungsten structure below the third portion of the third copper structure and interfacing the second drain region, wherein the first portion of the third copper structure is formed directly on the first tungsten structure, the second portion of the third copper structure is formed directly on the second tungsten structure and the third portion of the third copper structure interfaces a sidewall of the first tungsten structure and interfaces a sidewall of the second tungsten structure adjacent to the third portion of the third copper structure interface with the top surface of the isolation structure.

10. The integrated circuit of claim 9 , wherein the second portion of the third copper structure interfaces lateral sidewalls of each of the first tungsten structure and the second tungsten structure.

11. The integrated circuit of claim 9 , wherein a top surface of each of the first, second and third portions of the third copper structure are coplanar.

12. The integrated circuit of claim 11 , wherein the top surface of each of the first, second and third portions of the third copper structure is coplanar with a top surface of the first copper structure and the second copper structure.

13. The integrated circuit of claim 9 , wherein D1 plus D2 is substantially equal to a first width of the first diffusion area in the routing direction.

14. The integrated circuit of claim 13 , wherein the D3 plus D4 is substantially equal to a second width of the second diffusion area in the routing direction.

15. The integrated circuit of claim 9 , wherein the first end and the fifth end are disposed over the first diffusion area and the third end and the sixth end are disposed over the second diffusion area.

16. An integrated circuit comprising:
a first diffusion area for a first type transistor, the first type transistor including a first drain region and a first sour

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Keshavarzi Ali
• Guo Ta-Pen
• Sung Shu-Hui
• Tseng Hsiang-Jen
• Lin Shyue-Shyh
• Lu Lee-Chung
• Wu Chung-Cheng
• Tien Li-Chun
• Yang Jung-Chan
• Chen ting yu
• Cao Min
• Hou Yung-Chin

Classifications

• H10W20/40

  Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes · CPC title

• H10D84/85 Primary

  Complementary IGFETs, e.g. CMOS · CPC title

• H10D89/10

  Integrated device layouts · CPC title

• H10D84/0186

  Manufacturing their interconnections or electrodes, e.g. source or drain electrodes · CPC title

• H10D84/038

  using silicon technology, e.g. SiGe · CPC title