Display device having a gate driver compensation circuit, and driving method thereof

Patent metadata

Field	Value
Publication number	US-11580911-B2
Application number	US-202117508651-A
Country	US
Kind code	B2
Filing date	Oct 22, 2021
Priority date	Oct 23, 2020
Publication date	Feb 14, 2023
Grant date	Feb 14, 2023

Abstract

A display device and a driving method thereof are discussed. The display device can include a display panel for displaying images, a scan driver for supplying scan signals to the display panel, and a gate compensation circuit. The gate compensation circuit is configured to respectively sense a first node voltage and a second node voltage from a first node controller and a second node controller of the scan driver, and change a turn-on duty ratio of the first node controller to the second node controller based on the sensed first node voltage and second node voltage.

First claim

What is claimed is:

1. A display device, comprising:
a display panel configured to display images;
a scan driver configured to supply scan signals to the display panel; and
a gate compensation circuit configured to respectively sense a first node voltage and a second node voltage from a first node controller and a second node controller of the scan driver, and change a turn-on duty ratio of the first node controller to the second node controller based on the sensed first node voltage and second node voltage,
wherein the gate compensation circuit is configured to determine a degree of deterioration of pull-down transistors included in the first node controller and the second node controller based on averages of logic high periods in the sensed first node voltage and second node voltage.

2. The display device of claim 1 , wherein the gate compensation circuit is configured to change levels of a first voltage applied to the first node controller and a second voltage applied to the second node controller based on the sensed first node voltage and second node voltage.

3. The display device of claim 2 , wherein the gate compensation circuit is configured to change at least one of the turn-on duty ratio of the first node controller to the second node controller and a level change rate of the first voltage and the second voltage depending on a on the degree of deterioration of pull-down transistors controlled by the control of the first node controller and the second node controller.

4. The display device of claim 2 , wherein the gate compensation circuit includes:
an analog-to-digital converter configured to convert the sensed first node voltage and second node voltage into digital forms and output the first and second node voltages in the digital forms as node voltage sensing values, and
a voltage controller configured to determine deterioration of pull-down transistors based on the node voltage sensing values and generate at least one of a duty change signal and a level change signal depending on the degree of deterioration of pull-down transistors.

5. The display device of claim 4 , wherein the gate compensation circuit further includes:
a scaler configured to reduce levels of the sensed first node voltage and second node voltage and then transmit the first node voltage and the second node voltage to the analog-to-digital converter.

6. The display device of claim 4 , wherein the gate compensation circuit is configured to:
transmit the duty change signal to a level shifter included in the scan driver, and
transmit the level change signal to a power supply providing a voltage to the level shifter.

7. The display device of claim 1 , wherein the gate compensation circuit is configured to:
sense respectively a first gate high voltage and a second gate high voltage for controlling gate electrodes of a first pull-down transistor and a second pull-down transistor included in the scan driver, and
change a compensation rate depending on the degree of deterioration of the first pull-down transistor and the second pull-down transistor.

8. A method of driving the display device of claim 1 including the scan driver, the method comprising:
alternately charging a first gate high voltage and a second gate high voltage in the first node controller and the second node controller of the scan driver;
sensing the first node voltage from the first node controller and sensing the second node voltage from the second node controller;
determining the degree of deterioration of a first pull-down transistor and a second pull-down transistor of the pull-down transistors included in the scan driver based on the sensed first node voltage and second node voltage; and
charging the turn-on duty ratio of the first node controller to the second node controller depending on the degree of deterioration of the first pull-down transistor and the second pull-down transistor.

9. The method of claim 8 , wherein the changing the turn-on duty ratio further comprises:
changing levels of the first gate high voltage and the second gate high voltage depending on the degree of deterioration of the first pull-down transistor and the second pull-down transistor.

10. The method of claim 9 , wherein the changing the turn-on duty ratio comprises:
changing at least one of the turn-on duty ratio of the first node controller to the second node controller and a level change rate of the first gate high voltage and the second gate high voltage depending on the degree of deterioration of the first pull-down transistor and the second pull-down transistor.

Assignees

• Lg Display Co Ltd

Inventors

• Hong Moo Kyoung
• Yang Jong Won

Classifications

• G09G3/32 Primary

  semiconductive, e.g. using light-emitting diodes [LED] · CPC title

• G09G2310/08

  Details of timing specific for flat panels, other than clock recovery · CPC title

• G09G3/3208

  organic, e.g. using organic light-emitting diodes [OLED] · CPC title

• G09G2310/0289

  Details of voltage level shifters arranged for use in a driving circuit · CPC title

• G09G2300/0838

  with level shifting · CPC title