Shift register

Patent metadata

Field	Value
Publication number	US-9293222-B2
Application number	US-201414308577-A
Country	US
Kind code	B2
Filing date	Jun 18, 2014
Priority date	Jun 21, 2013
Publication date	Mar 22, 2016
Grant date	Mar 22, 2016

Abstract

Disclosed is a shift register capable of stably generating an output even when the threadhold voltage of a pull-down switching element is raised due to degradation of the pull-down switching element. The shift register includes a plurality of stages each comprising a node controller comprising an inverter to control a voltage at a reset node in accordance with a voltage at a set node, and an output unit to output a scan pulse based on at least one of the voltage at the set node and the voltage at the reset node. The shift register further includes an inverter voltage controller for controlling a high-level inverter voltage supplied to each inverter of the stages based on the voltage at at least one reset node in at least one of the stages.

First claim

What is claimed is:

1. A shift register comprising:
a plurality of stages, each stage comprising a node controller and an output unit, the node controller including an inverter controlling a voltage at a reset node in accordance with a voltage at a set node, and the output unit outputting a scan pulse based on at least one of the voltage at the set node and the voltage at the reset node; and
an inverter voltage controller for controlling a high-level inverter voltage supplied to the inverter of each of the plurality of stages based on the voltage at at least one reset node in at least one of the stages.

2. The shift register according to claim 1 , wherein the inverter voltage controller comprises:
a voltage monitor for adjusting a level of a monitoring voltage in accordance with a level of a voltage applied to the reset node, and outputting the adjusted monitoring voltage to a monitoring input line; and
a voltage adjuster including a comparator adjusting a level of the high-level inverter voltage based on the monitoring voltage applied to the monitoring input line and a predetermined reference voltage, and supplying the adjusted high-level inverter voltage to the inverter.

3. The shift register according to claim 2 , wherein the voltage monitor comprises:
at least one monitoring switching element controlled in accordance with the voltage at the reset node, and coupled between the monitoring input line and a first base voltage line to transmit a first base voltage to the monitoring input line; and
a resistor coupled between the monitoring input line and a second base voltage line to transmit a second base voltage to the monitoring input line,
wherein the resistor is one of a variable resistor and a switching element.

4. The shift register according to claim 3 , wherein:
the at least one monitoring switching element comprises two or more monitoring switching elements;
gate electrodes of the two or more monitoring switching elements are coupled to one of the reset node of the corresponding stage and reset nodes in two or more of the stages; and
the two or more monitoring switching elements are coupled in parallel between the monitoring input line and the first base voltage line.

5. The shift register according to claim 2 , wherein the voltage adjuster further comprises one of:
a first capacitor coupled between an output terminal of the comparator and the monitoring input line, and
a level converter being one of a level shifter, a DC-DC converter and an amplifier which shifts the level of the high-level inverter voltage output from the comparator,
wherein the inverter voltage controller further comprises a second capacitor coupled between the monitoring input line and a low voltage transmission line to transmit a low voltage to the monitoring input line.

6. The shift register according to claim 1 ,
wherein the output unit comprises:
a pull-up switching element controlled in accordance with the voltage at the set node, and coupled between a clock transmission line and an output terminal to transmit a clock pulse to the output terminal; and
a pull-down switching element controlled in accordance with the voltage at the reset node, and coupled between the output terminal and a first discharge voltage line to transmit a first discharge voltage to the output terminal,
wherein the node controller comprises a first switching element and a second switching element, wherein:
the first switching element is controlled in accordance with a start pulse or a scan pulse from a prior stage of the stages, and coupled to a charge voltage line to transmit a charge voltage while being coupled to the set node; and
the second switching element is controlled in accordance with a scan pulse from a next stage of the stages, and coupled between the set node and a first discharge voltage line to transmit a first discharge voltage to the set node.

7. The shift register according to claim 6 , wherein the node controller further comprises a third switching element, the third switching element controlled in accordance with the voltage at the reset node of the selected stage and coupled between the set node of the selected stage and the first discharge voltage line to transmit the first discharge voltage to the set node of the selected stage.

8. The shift register according to claim 1 , wherein the inverter comprises:
a first inversion switching element controlled in accordance with the high-level inverter voltage applied to a high-level inverter line after being output from the inverter voltage controller, the first inversion switching element coupled between the high-level inverter line and a common node;
a second inversion switching element controlled in accordance with the voltage at the set node, the second inversion switching element coupled between the common node and a low-level inverter line to transmit a low-level inverter voltage to the common node;
a third inversion switching element controlled in accordance with a voltage at the common node, the third inversion switching element coupled between the high-level inverter line and the reset node; and
a fourth inversion switching element controlled in accordance with the voltage at the set node, the fourth inversion switching element coupled between the reset node and the low-level inverter line.

9. The shift register according to claim 8 , wherein:
the inverter further comprises one of:
a first structure comprising a fifth inversion switching element controlled in accordance with a scan pulse from a prior stage of the stages, the fifth inversion switching element coupled between the reset node and the low-level inverter line to transmit the low-level inverter voltage,
a second structure comprising a sixth inversion switching element controlled in accordance with the voltage at the reset node, the sixth inversion switching element coupled between the set node and one of the low-level inverter line and an output terminal of the corresponding stage,
a third structure comprising a seventh inversion switching element controlled in accordance with the voltage at the reset node, the seventh inversion switching element coupled between the set node and a fourth clock transmission line to transmit a fourth clock pulse to the set node,
a fourth structure comprising an eighth inversion switching element controlled in accordance with a fifth clock pulse from a fifth clock transmission line, the eighth inversion switching element coupled between an output terminal of the prior stage and the set node,
a fifth structure comprising a ninth inversion switching element controlled in accordance with a scan pulse from the corresponding stage, the ninth inversion switching element coupled between the reset node in the selected stage and the low-level inverter line, and
a sixth structure comprising a tenth inversion switching element, an eleventh inversion switching element, and a third capacitor, wherein:

the tenth inversion switching element is controlled in accordance with the voltage at the set node and is coupled between the reset node in the selected stage and the low-level inverter line,
the eleventh inversion switching element is controlled in accordance with the voltage at the reset node and is coupled between the set node and the output terminal of the prior stage,
the third capacitor is coupled between the fifth clock transmission line and the reset node,
the fifth clock pulse is a clock pulse used as the scan pulse of the prior stage; and
the fourth clock pulse is used as the scan pulse of the corresponding stage.

10. The shift register according to claim 1 , wherein:
the reset node is divided into a first reset node and a second reset node;
the inverter i

Assignees

• Lg Display Co Ltd

Inventors

• Jang Yong-Ho
• Kim Cheol-Se

Classifications

• G09G2310/0286

  Details of a shift registers arranged for use in a driving circuit · CPC title

• G11C19/28 Primary

  using semiconductor elements (G11C19/14, G11C19/36 take precedence) · CPC title

• G11C19/00 Primary

  Digital stores in which the information is moved stepwise, e.g. shift registers · CPC title

• G09G3/36

  using liquid crystals · CPC title