Symmetry unary code encoder

Patent metadata

Field	Value
Publication number	US-11575387-B2
Application number	US-201916709622-A
Country	US
Kind code	B2
Filing date	Dec 10, 2019
Priority date	Dec 10, 2019
Publication date	Feb 7, 2023
Grant date	Feb 7, 2023

Abstract

An encode apparatus and an encode method may be provided. The encoding apparatus may comprise a first stage and a second stage. The first stage may be configured to receive a first input, decode the first input, and produce a first output comprising the decoded first input. The second stage may be configured to receive a second input, receive the first output from the first stage, and convert the first input and the second input from a first coding system to a second coding system based on the second input and the first output. The second stage may produce a second output comprising the converted first input and the converted second input.

First claim

What is claimed is:

1. An apparatus comprising:
a first stage configured to;
receive a first input,
decode the first input, and
produce a first output comprising the decoded first input; and

a second stage configured to;
receive a second input,
receive the first output from the first stage,
convert the first output and the second input from a first code to a second code based on the second input and the first output wherein the first code comprises one of Binary Code and Gray Code and wherein the second code comprises Unary Code, and
produce a second output comprising the converted first output and the converted second input.

2. The apparatus of claim 1 , wherein the second stage comprises a plurality of logic gates.

3. The apparatus of claim 2 , wherein the decoder comprises a 7:1 decoder.

4. The apparatus of claim 3 , wherein the second stage comprises a first plurality of two input port AND gates, each one of the first plurality of two input port AND gates having a first input port respectively connected to one of seven output nodes of the 7:1 decoder and a second input port connected to an inverse of an input bit.

5. The apparatus of claim 4 , wherein the second stage comprises a second plurality of two input port AND gates, each one of the second plurality of two input port AND gates having a first input port respectively connected to one of the seven output nodes of the 7:1 decoder and a second input port connected to an input bit.

6. The apparatus of claim 5 , wherein inputs to the first plurality of two input port AND gates and the second plurality of two input port AND gates are arranged to reduce standby current for more commonly occurring TRIM codes used in a sense amplifier (SA) trimming function.

7. The apparatus of claim 1 , wherein the first stage comprises a decoder that produces the first output that is smaller than the second output.

8. The apparatus of claim 1 , wherein the apparatus is disposed in a Magnetoresistive Random Access Memory (MRAM).

9. The apparatus of claim 8 , wherein the second output corresponds to trim codes used in a sense amplifier (SA) trimming function of the MRAM.

10. An apparatus comprising:
a first stage comprising a 7:1 decoder configured to:
receive a first input comprising a 0 th bit, a 1 st bit, and a 2 nd bit of an input code,
decode the first input, and
produce a first output comprising the decoded first input on seven output nodes on the 7:1 decoder; and

a second stage comprising:
a second stage input port configured to receive a 3 rd bit of the input code,
a first plurality of two input port AND gates, each one of the first plurality of two input port AND gates having a first input port respectively connected to one of the seven output nodes of the 7:1 decoder and a second input port connected to an inverse of the 3 rd bit of the input code,
a second plurality of two input port AND gates, each one of the second plurality of two input port AND gates having a first input port respectively connected to one of the seven output nodes of the 7:1 decoder and a second input port connected to the 3 rd bit of the input code, and
a 15 bit output, wherein bits 1 through 7 of the 15 bit output respectively correspond to outputs of the first plurality of two input port AND gates, bits 9 through 15 of the 15 bit output respectively correspond to outputs of the second plurality of two input port AND gates, and bit 8 of the 15 bit output corresponds to the second stage input port.

11. The apparatus of claim 10 , wherein the input code comprises Gray Code.

12. The apparatus of claim 10 , wherein the input code comprises Binary Code.

13. The apparatus of claim 10 , wherein the 15 bit output comprises Unary Code.

14. The apparatus of claim 10 , wherein the apparatus is disposed in a Magnetoresistive Random Access Memory (MRAM).

15. The apparatus of claim 14 , wherein the 15 bit output corresponds to trim codes used in a sense amplifier (SA) trimming function of the MRAM.

16. A method comprising:
receiving a 0th bit, a 1st bit, a 2nd bit, and a 3rd bit of an input code;
decoding the 0th bit, the 1st bit, and the 2nd bit of the input code to create a first output;
generating a first portion of a second output based on the 3rd bit of the input code and the first output;
generating a second portion of the second output based on the 3rd bit of the input code and the first output; and
generating a third portion of the second output comprising the 3rd bit of the input code.

17. The method of claim 16 , wherein generating the first portion of the second output comprises ANDing an inverse of the 3rd bit with the first output.

18. The method of claim 16 , wherein generating the second portion of the second output comprises ANDing the 3rd bit with the first output.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Khwa Win-San
• Noguchi Hiroki
• Lin Ku-Feng

Classifications

• G11C11/1673

  Reading or sensing circuits or methods · CPC title

• G11C29/021

  in voltage or current generators · CPC title

• G11C11/161 Primary

  details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell · CPC title

• H03K19/20 Primary

  characterised by logic function, e.g. AND, OR, NOR, NOT circuits (H03K19/003 - H03K19/01 take precedence) · CPC title

• H03M7/16 Primary

  Conversion to or from unit-distance codes, e.g. Gray code, reflected binary code · CPC title