Transimpedance amplifiers with adjustable input range

Patent metadata

Field	Value
Publication number	US-11575355-B2
Application number	US-202217575788-A
Country	US
Kind code	B2
Filing date	Jan 14, 2022
Priority date	Sep 25, 2019
Publication date	Feb 7, 2023
Grant date	Feb 7, 2023

Abstract

A multi-stage transimpedance amplifier (TIA) with an adjustable input linear range is disclosed. The TIA includes a first stage, configured to convert a single-ended current signal from an optical sensor of a receiver signal chain to a single-ended voltage signal, and a second stage, configured to convert the single-ended voltage signal provided by the first stage to a differential signal. In such a TIA, the input linear range may be adjusted using a clamp that is programmable with an output offset current to keep the second stage of the TIA from overloading and to maintain a linear transfer function without compression.

First claim

The invention claimed is:

1. A system for converting a single-ended current input to a differential voltage output, the system comprising:
an amplifier circuit, comprising a first transistor and a second transistor, the amplifier circuit to generate an output based on the single-ended current input and having an output terminal for providing the output; and
a third transistor, coupled to the output terminal,
wherein:
each of the first transistor, the second transistor, and the third transistor includes a first terminal, a second terminal, and a third terminal,
the second terminal of the first transistor is coupled to the third terminal of the second transistor,
the amplifier circuit is to receive the single-ended current input at the third terminal of the first transistor,
the first terminal of the second transistor is coupled to the output terminal of the amplifier circuit,
the first terminal of the third transistor is coupled to the third terminal of the second transistor, and
the system is to generate the differential voltage output based on the output generated by the amplifier circuit.

2. The system according to claim 1 , wherein:
the first terminal of the third transistor is coupled to the first terminal of the second transistor.

3. The system according to claim 1 , wherein:
the second terminal of the first transistor is further coupled to the first terminal of the third transistor.

4. The system according to claim 1 , further comprising a feedback component, wherein:
a first terminal of the feedback component is coupled to the third terminal of the first transistor, and
a second terminal of the feedback component is coupled to the first terminal of the second transistor.

5. The system according to claim 4 , wherein the feedback component is a resistor.

6. The system according to claim 4 , wherein:
the second terminal of the third transistor is coupled to a control signal, and
the control signal is based on a resistance of a feedback component.

7. The system according to claim 1 , wherein:
the second terminal of the third transistor is coupled to a control signal, and
the control signal is based on at least one of:
a voltage difference between the first terminal and the third terminal of the first transistor, and
a voltage difference between the first terminal and the third terminal of the second transistor.

8. The system according to claim 1 , wherein:
when each of the first transistor, the second transistor, and the third transistor is a bipolar junction transistor, the first terminal is an emitter terminal, the second terminal is a collector terminal, and the third terminal is a base terminal, and
when each of the first transistor, the second transistor, and the third transistor is a field-effect transistor, the first terminal is a source terminal, the second terminal is a drain terminal, and the third terminal is a gate terminal.

9. The system according to claim 1 , wherein the system is a driver for an analog-to-digital converter.

10. The system according to claim 1 , wherein the system is a light detection and ranging (LIDAR) system.

11. A method for operating a system that includes a first amplifier circuit, a second amplifier circuit, a third amplifier circuit, and a clamp circuit, the method comprising:
operating the first amplifier circuit to generate a first amplifier output based on a single-ended current input;
providing a signal based on an output offset current to each of an input of second amplifier circuit and an input of the clamp circuit;
operating the second amplifier circuit to generate a second amplifier output based on the output offset current;
operating the clamp circuit, coupled to an output of the first amplifier circuit and to a control signal, to set one of a minimum voltage value or a maximum voltage value for the first amplifier output based on the signal provided to the input of the clamp circuit; and
operating the third amplifier circuit to generate a differential output based on a signal based on the second amplifier output and a signal based on the first amplifier output that abides by the minimum voltage value or the maximum voltage value set for the first amplifier output by the clamp circuit.

12. The method according to claim 11 , wherein:
the first amplifier circuit includes a first transistor and a second transistor,
the clamp circuit includes a third transistor,
each of the first transistor, the second transistor, and the third transistor includes a first terminal, a second terminal, and a third terminal,
the first terminal of the third transistor is coupled to the third terminal of the second transistor,
the first terminal of the second transistor is coupled to the output of the first amplifier circuit,
the first amplifier circuit is to receive the single-ended current input at the third terminal of the first transistor, and
the second terminal of the first transistor is coupled to the third terminal of the second transistor.

13. The method according to claim 11 , wherein:
the first amplifier circuit includes a first transistor and a second transistor,
the clamp circuit includes a third transistor,
the control signal is to set the maximum voltage value,
each of the first transistor and the second transistor is an N-type transistor, and
the third transistor is a P-type transistor.

14. The method according to claim 13 , wherein the control signal is based on a positive supply voltage for the first amplifier circuit and the clamp circuit.

15. The method according to claim 11 , wherein:
the first amplifier circuit includes a first transistor and a second transistor,
the clamp circuit includes a third transistor,
the control signal is to set the minimum voltage value,
each of the first transistor and the second transistor is a P-type transistor, and
the third transistor is an N-type transistor.

16. The method according to claim 15 , wherein the control signal is based on a negative supply voltage for the first amplifier circuit and the clamp circuit.

17. The method according to claim 11 , wherein:
the first amplifier circuit includes a transistor, and
the control signal is to set one of the minimum voltage value or the maximum voltage value for the first amplifier output further based on:
a voltage difference between an emitter terminal and a base terminal of the transistor when the transistor is a bipolar junction transistor, or
a voltage difference between a source terminal and a gate terminal of the transistor when the transistor is a field-effect transistor.

18. The method according to claim 11 , wherein:
the system further includes a feedback component having a first terminal coupled to the third terminal of the first transistor and having a second terminal coupled to the first terminal of the second transistor, and
the control signal is to set one of the minimum voltage value or the maximum voltage value for the first amplifier output further based on a resistance of the feedback component.

19. A system to generate a differential output based on a signal input, comprising:
a first amplifier circuit, to generate an output based on the signal input;
a clamp circuit, to clamp the output of the first amplifier circuit based on an amplitude of the output of the first amplifier circuit and further based on an offset current;
a second amplifier circuit, to generate an output based on the offset current, the second amplifier circuit being a replica of the first amplifier circuit; and
a third amplifier circu

Assignees

• Analog Devices International Unlimited Co

Inventors

• Adut Joseph
• Wong Jeremy
• Cheung Eugene L
• Hamilton Brian D
• Fung Gregory A

Classifications

• H03F1/34

  Negative-feedback-circuit arrangements with or without positive feedback (H03F1/02 - H03F1/30, H03F1/38 - H03F1/50, H03F3/50 take precedence {; for rejection of common mode signals H03F3/45479}) · CPC title

• H03F1/083

  in transistor amplifiers (H03F1/10 - H03F1/22 take precedence) · CPC title

• H03F3/087 Primary

  with IC amplifier blocks (H03F3/085 takes precedence) · CPC title

• H03F3/456

  by using a feedback circuit · CPC title

• H03F3/45973

  by using a feedback circuit · CPC title