Semiconductor device having high voltage transistors

Patent metadata

Field	Value
Publication number	US-11575009-B2
Application number	US-202016822389-A
Country	US
Kind code	B2
Filing date	Mar 18, 2020
Priority date	Jul 23, 2019
Publication date	Feb 7, 2023
Grant date	Feb 7, 2023

Abstract

A semiconductor device includes a gate structure disposed on a substrate. The gate structure has a first sidewall and a second sidewall facing the first sidewall. A first impurity region is disposed within an upper portion of the substrate. The first impurity region is spaced apart from the first sidewall. A third impurity region is within the upper portion of the substrate. The third impurity region is spaced apart from the second sidewall. A first trench is disposed within the substrate between the first sidewall and the first impurity region. The first trench is spaced apart from the first sidewall. A first barrier insulation pattern is disposed within the first trench.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a gate structure disposed on a substrate, the gate structure having a first sidewall and a second sidewall facing the first sidewall;
a first impurity region disposed within an upper portion of the substrate, the first impurity region being spaced apart from the first sidewall;
a third impurity region disposed within the upper portion of the substrate, the third impurity region being spaced apart from the second sidewall;
a first trench disposed within the substrate between the first sidewall and the first impurity region, the first trench being spaced apart from the first sidewall;
a first barrier insulation pattern disposed in the first trench;
a second trench disposed within the substrate between the second sidewall and the third impurity region, the second trench being spaced apart from the second sidewall; and
a second barrier insulation pattern disposed in the second trench,
wherein the first impurity region constitutes a first source/drain region,
wherein the third impurity region constitutes a second source/drain region,
wherein the first trench, that is spaced apart from the first sidewall, is disposed between the gate and the first source/drain region,
wherein the second trench, that is spaced apart from the second sidewall, is disposed between the gate and the second source/drain region,
a second impurity region formed within the substrate between the first sidewall and the first impurity region and extending along a surface of the first trench, the second impurity region being connected to the first impurity region and having at least one horizontal section that is disposed between the first trench and the first sidewall or between the first trench and the first impurity region, and
a fourth impurity region formed within the substrate between the second sidewall and the third impurity region and extending along a surface of the second trench, the fourth impurity region being connected to the third impurity region and having at least one horizontal section that is disposed between the second trench and the second sidewall or between the second trench and the third impurity region.

2. The semiconductor device of claim 1 , wherein the second impurity region is formed along a surface of the substrate contacting the first harrier insulation pattern.

3. The semiconductor device of claim 1 , wherein impurity concentrations of the first and third impurity regions are higher than impurity concentrations of the second and fourth impurity regions.

4. The semiconductor device of claim 1 , wherein the first, second, third and fourth impurity, regions are all doped with impurities having a same conductivity type.

5. The semiconductor device of claim 1 , wherein the fourth impurity region is formed along the substrate under the surface of the second barrier insulation pattern.

6. The semiconductor device of claim 1 , wherein a distance between the first sidewall and the first trench is the same as a distance between the second sidewall and the second trench.

7. The semiconductor device of claim 1 , wherein an upper surface of the substrate between the second sidewall and the third impurity region is flat.

8. The semiconductor device of claim 1 , wherein the gate structure includes a gate insulation pattern and a gate pattern stacked on the gate insulation pattern.

9. The semiconductor device of claim 1 , wherein the substrate further includes an isolation pattern, and the first impurity region and/or third impurity region contacts the isolation pattern.

10. The semiconductor device of claim 1 , further comprising a spacer formed on the first sidewall of the gate structure.

11. The semiconductor device of claim 1 , wherein a bottom of the spacer is overlapped by an upper portion of the first trench, or is not overlapped by the upper portion of the first trench.

12. A semiconductor device, comprising:
a gate structure formed on a substrate,
a first impurity region formed within the substrate, the first impurity region being spaced apart from a first sidewall of the gate structure;
a second purity region formed within the substrate between the first sidewall and the first impurity region, the second impurity region being connected to the first impurity region;
a third impurity region formed within the substrate, the third impurity region being spaced apart from a second sidewall facing the first sidewall of the gate structure;
a fourth impurity region formed within the substrate, between the second sidewall and the third impurity region, the fourth impurity region being connected to the third impurity region; and
a first barrier insulation pattern filling a first trench formed within the substrate, between the first sidewall and the first impurity region;
a second trench formed within the substrate between the second sidewall and the third impurity region, the second trench being spaced apart from the second sidewall; and
a second barrier insulation pattern disposed in the second trench,
wherein the first barrier insulation pattern is spaced apart from the first sidewall of the gate structure, and the second impurity region is formed along a surface of the substrate contacting the first barrier insulation pattern,
wherein the first impurity region constitutes a first source/drain regions,
wherein the third impurity region constitutes a second source/drain region,
wherein the first trench, that is spaced apart from the first sidewall, is disposed between the gate and the first source/drain region,
wherein the second trench, that is spaced apart from the second sidewall, is disposed between the gate and the second source/drain region,
wherein the second impurity region extends along a surface of the first trench and has at least one horizontal section that is disposed between the first trench and the first sidewall or between the first trench and the first impurity region, and
wherein the fourth impurity region extends along a surface of the second trench and has at least one horizontal section that is disposed between the second trench and the second sidewall or between the second trench and the third impurity region.

13. The semiconductor device of claim 12 , wherein the fourth impurity region is formed at an upper flat portion of the substrate between the second sidewall of the gate structure and the third impurity region.

14. The semiconductor device of claim 12 , wherein the fourth impurity region is formed along the surface of the substrate contacting the surface of the second barrier insulation pattern.

15. The semiconductor device of claim 14 , wherein a bottom of the first barrier insulation pattern and a bottom of the second barrier insulation pattern are positioned on different planes.

16. A semiconductor device, comprising:
a gate structure formed on the substrate;
a first impurity region formed at an upper portion of the substrate, the first impurity region being spaced apart from a first sidewall of the gate structure;
a second impurity region formed within the substrate, between the first sidewall and the first impurity region, the second impurity region being connected to the first impurity region;
a third impurity region formed at an upper portion of the substrate, the third impurity region being spaced apart from a second sidewall facing the first sidewall of the gate structure;
a fourth impurity region formed within the substrate between the second sidewall and the third impurity region, the fourth impurity region being connected to the third impurity region;
a first barrier insulation patte

Assignees

• Samsung Electronics Co Ltd

Inventors

• Baek Sungkweon
• Kim Taeyoung
• KIM Hakseon
• Yun Kangoh
• Jeon Changhoon
• Lim Junhee

Classifications

• H10D30/603

  having asymmetry in the channel direction, e.g. lateral high-voltage MISFETs having drain offset region or extended drain IGFETs [EDMOS] · CPC title

• H10D30/0411

  of FETs having floating gates · CPC title

• H10D64/021

  using multiple gate spacer layers, e.g. bilayered sidewall spacers · CPC title

• H10D64/513

  within recesses in the substrate, e.g. trench gates, groove gates or buried gates · CPC title

• H10D30/6891

  characterised by the shapes, relative sizes or dispositions of the floating gate electrode · CPC title