Field plate in heterojunction bipolar transistor with improved break-down voltage

Patent metadata

Field	Value
Publication number	US-9324846-B1
Application number	US-201514591946-A
Country	US
Kind code	B1
Filing date	Jan 8, 2015
Priority date	Jan 8, 2015
Publication date	Apr 26, 2016
Grant date	Apr 26, 2016

Abstract

A method of forming a heterojunction bipolar transistor including a field plate. The method may include forming: a substrate having a selectively implanted collector (SIC) and a collector separated by a shallow trench isolation (STI), a field plate in the STI, the field plate extends below a top surface of the SIC, a base layer directly on the SIC, a heterojunction bipolar transistor (HBT) structure above the SIC, the HBT includes an emitter, the emitter is directly on the base layer, a fourth dielectric layer covering the HBT structure, the field plate and the collector, and an emitter contact, a field plate contact and a collector contact extending through the fourth dielectric layer, the emitter contact is in electrical connection with the emitter, the field plate contact is in electrical connection with the field plate and the collector contact is in electrical connection with the collector.

First claim

What is claimed is:

1. A method comprising:
forming a substrate having a selectively implanted collector (SIC) and a collector separated by a shallow trench isolation (STI), a top portion of the STI is above the SIC and above the collector;
forming a trench in the STI, the trench has a first depth;
forming a sidewall spacer on sidewalls of the trench;
recessing the trench to a second depth and a portion of the SIC is exposed by the trench;
removing a portion of the exposed SIC in an undercut region of the SIC;
forming a trench barrier in the undercut region, the trench barrier is on all exposed surfaces of the SIC in the undercut region;
forming a field plate in the trench, the field plate extends into the undercut region, and the trench barrier is between the SIC and the field plate;
forming a base layer above the SIC and above the field plate, the base layer is directly on top of the SIC;
forming a heterojunction bipolar transistor (HBT) structure above the SIC, the HBT includes an emitter, the emitter is directly on top of the base layer;
forming a fourth dielectric layer covering the HBT structure, the field plate and the collector; and
forming an emitter contact, a field plate contact and a collector contact through the fourth dielectric layer, the emitter contact is in electrical connection with the emitter, the field plate contact is in electrical connection with the field plate, and the collector contact is in electrical connection with the collector.

2. The method of claim 1 , further comprising:
forming a second dielectric on a coplanar top surface of the field plate and the STI, the second dielectric is between the base layer and the field plate, and the top portion of the STI above the SIC is not covered by the second dielectric.

3. The method of claim 1 , further comprising:
forming an extrinsic base layer on the base layer, wherein a portion of the HBT is above the extrinsic base layer and the emitter extends through the extrinsic base layer.

4. The method of claim 1 , further comprising:
forming a base contact through the fourth dielectric layer, the base contact is in electrical connection with the base layer, wherein the base layer is not in electrical connection with the field plate.

5. The method of claim 1 , wherein the field plate contact is in electrical connection with the base layer and the field plate.

6. The method of claim 1 , wherein the undercut region has an undercut profile, and wherein the undercut profile is a box-like profile, a lateral triangular profile, a lateral diamond profile, or a tapered profile.

7. The method of claim 1 , wherein the STI and the trench barrier are oxides, the base layer includes germanium and silicon-germanium, the field plate and the emitter are poly-silicon, and the substrate is silicon.

8. A method comprising:
forming a substrate having a selectively implanted collector (SIC) and a collector separated by a shallow trench isolation (STI), a top portion of the STI is above the SIC and above the collector;
forming a trench in the STI, the trench does not reach the SIC;
forming a field plate in the trench;
forming a base layer above the SIC and above the field plate, the base layer is directly on top of the SIC;
forming a heterojunction bipolar transistor (HBT) structure above the SIC, the HBT includes an emitter, the emitter is directly on the base layer, and a portion of the field plate is below a bottom surface plane of the HBT structure;
forming a fourth dielectric layer covering the HBT structure, the field plate and the collector; and
forming an emitter contact, a field plate contact and a collector contact through the fourth dielectric layer, the emitter contact is in electrical connection with the emitter, the field plate contact is in electrical connection with the field plate, and the collector contact is in electrical connection with the collector.

9. The method of claim 8 , further comprising:
forming a second dielectric on a coplanar top surface of the field plate and the STI, the second dielectric is between the base layer and the field plate, and the top portion of the STI above the SIC is not covered by the second dielectric.

10. The method of claim 8 , further comprising:
forming an extrinsic base layer on the base layer, wherein a portion of the HBT is above the extrinsic base layer and the emitter extends through the extrinsic base layer.

11. The method of claim 8 , further comprising:
forming a base contact through the fourth dielectric layer, the base contact is in electrical connection with the base layer, wherein the base layer is not in electrical connection with the field plate.

12. The method of claim 8 , wherein the field plate contact is in electrical connection with the base layer and the field plate.

13. The method of claim 8 , wherein the STI is an oxide, the base layer includes germanium and silicon-germanium, the field plate and the emitter are poly-silicon, and the substrate is silicon.

14. A structure comprising:
a substrate having a selectively implanted collector (SIC) and a collector separated by a shallow trench isolation (STI);
a field plate in the STI, the field plate extends below a top surface of the SIC;
a base layer directly on the SIC;
a heterojunction bipolar transistor (HBT) structure above the SIC, the HBT includes an emitter, the emitter is directly on the base layer;
a fourth dielectric layer covering the HBT structure, the field plate and the collector; and
an emitter contact, a field plate contact and a collector contact extending through the fourth dielectric layer, the emitter contact is in electrical connection with the emitter, the field plate contact is in electrical connection with the field plate and the collector contact is in electrical connection with the collector.

15. The structure of claim 14 , wherein the field plate extends into an undercut region in the SIC, further comprising:
a trench barrier in the undercut region, the trench barrier is between the field plate and the SIC.

16. The structure of claim 15 , wherein the undercut region has an undercut surface having an undercut profile, and wherein the undercut profile is a box-like profile, a lateral triangular profile, a lateral diamond profile, or a tapered profile.

17. The structure of claim 14 , further comprising:
a second dielectric layer between the field plate and the base layer.

18. The structure of claim 14 , further comprising:
an extrinsic base layer on top of the base layer, wherein the extrinsic base layer is poly-silicon.

19. The structure of claim 14 , further comprising:
a base contact extending through the fourth dielectric layer, the base contact is in electrical connection with the base layer, wherein the base layer is not in electrical connection with the field plate.

20. The structure of claim 14 , wherein the field plate contact is in electrical connection with the base layer and the field plate.

Assignees

• IBM
• Globalfoundries Inc

Inventors

• Camillo-Castillo Renata A
• Jain Vibhor
• Khater Marwan H
• Sharma Santosh

Classifications

• H10P30/204

  into Group IV semiconductors · CPC title

• H10P30/21

  of electrically active species · CPC title

• H10D64/62

  Electrodes ohmically coupled to a semiconductor · CPC title

• H10D62/822

  comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions · CPC title

• H10D64/281

  Base electrodes for bipolar transistors · CPC title