Semiconductor package

Patent metadata

Field	Value
Publication number	US-11574856-B2
Application number	US-202117221597-A
Country	US
Kind code	B2
Filing date	Apr 2, 2021
Priority date	May 22, 2018
Publication date	Feb 7, 2023
Grant date	Feb 7, 2023

Abstract

A semiconductor package includes a base material, a capture land, an interconnection structure, a semiconductor chip and an encapsulant. The base material has a top surface and an inner lateral surface. The capture land is disposed in or on the base material, and has an outer side surface. The interconnection structure is disposed along the inner lateral surface of the base material, and on the capture land. The interconnection structure has an outer side surface. An outer side surface of the semiconductor package includes the outer side surface of the capture land and the outer side surface of the interconnection structure. The semiconductor chip is disposed on the top surface of the base material. The encapsulant is disposed adjacent to the top surface of the base material, and covers the semiconductor chip.

First claim

What is claimed is:

1. A substrate, comprising:
a capture land;
an interconnection structure contacting the capture land;
a base material contacting the capture land and the interconnection structure; and
a circuitry structure contacting the base material and electrically connected to the capture land through the interconnection structure,
wherein the interconnection structure and the circuitry structure jointly define a recess portion, the circuitry structure has an arc-shaped surface exposed in the recess portion, and the arc-shaped surface of the circuitry structure extends downward and outward.

2. The substrate of claim 1 , wherein the arc-shaped surface of the circuitry structure extends downward and outward from a top surface of the circuitry structure to a bottom surface of the circuitry structure.

3. The substrate of claim 1 , wherein the circuitry structure includes a taper portion below the interconnection structure, and the taper portion of the circuitry structure tapers upward from a bottom surface of the circuitry structure.

4. The substrate of claim 1 , wherein an included angle between the arc-shaped surface of the circuitry structure and a bottom surface of the circuitry structure is less than an included angle between the arc-shaped surface of the circuitry structure and a top surface of the circuitry structure.

5. The substrate of claim 4 , wherein the included angle between the arc-shaped surface of the circuitry structure and the bottom surface of the circuitry structure is an acute angle.

6. The substrate of claim 4 , wherein the included angle between the arc-shaped surface of the circuitry structure and the top surface of the circuitry structure is an obtuse angle.

7. The substrate of claim 1 , wherein the interconnection structure has an arc-shaped surface exposed in the recess portion, and an included angle between the arc-shaped surface of the circuitry structure and a bottom surface of the circuitry structure is less than an included angle between the arc-shaped surface of the interconnection structure and a top surface of the circuitry structure.

8. The substrate of claim 7 , wherein the included angle between the arc-shaped surface of the circuitry structure and the bottom surface of the circuitry structure is an acute angle.

9. The substrate of claim 7 , wherein the interconnection structure has an arc-shaped surface exposed in the recess portion, and the included angle between the arc-shaped surface of the interconnection structure and the top surface of the circuitry structure is an obtuse angle.

10. The substrate of claim 1 , wherein a part of the recess portion is recessed from an outer side surface of the interconnection structure, the other part of the recess portion is recessed from an outer side surface of the circuitry structure, the interconnection structure has an arc-shaped surface exposed in the recess portion, and the recess portion is defined by the arc-shaped surface of the interconnection structure and the arc-shaped surface of the circuitry structure.

11. The substrate of claim 10 , wherein the arc-shaped surface of the interconnection structure and the arc-shaped surface of the circuitry structure constitute a continuous arc-shaped surface.

12. The substrate of claim 1 , wherein the capture land is embedded in the base material.

13. The substrate of claim 1 , wherein a top surface of the capture land is substantially coplanar with a top surface of the base material.

14. The substrate of claim 1 , wherein the interconnection structure has an arc-shaped surface exposed in the recess portion, and the arc-shaped surface of the circuitry structure is in a downward projection area of the arc-shaped surface of the interconnection structure.

15. The substrate of claim 1 , wherein an outer side surface of the encapsulant is substantially coplanar with an outer side surface of the interconnection structure and an outer side surface of the capture land.

16. The substrate of claim 1 , wherein the base material includes at least one first circuitry structure, the first circuitry structure includes at least one conductive trace, a first gap is between the conductive trace and the capture land, the circuitry structure has a portion corresponding to the first gap, a second gap is between the portion of the circuitry structure and a projection area of the capture land, and the second gap is less than the first gap.

17. A semiconductor package, comprising:
a capture land;
an interconnection structure contacting the capture land;
a base material contacting the capture land and the interconnection structure;
a circuitry structure contacting the base material and electrically connected to the capture land through the interconnection structure;
a semiconductor chip disposed adjacent to the top surface of the base material; and
an encapsulant disposed on the base material, and covering the semiconductor chip and the top surface of the capture land,
wherein the interconnection structure and the circuitry structure jointly define a recess portion, the circuitry structure has an arc-shaped surface exposed in the recess portion, and the arc-shaped surface of the circuitry structure extends downward and outward.

18. The semiconductor package of claim 17 , wherein the base material includes at least one dielectric structure and at least one first circuitry structure, and a portion of the dielectric structure is between the capture land and the first circuitry structure.

19. The semiconductor package of claim 18 , wherein a top surface of the first circuitry structure is substantially coplanar with a bottom surface of the encapsulant.

20. The semiconductor package of claim 18 , wherein the base material further includes a via structure electrically connected to the first circuitry structure, and a top surface of the via structure is between a top surface of the dielectric structure and a bottom surface of the dielectric structure.

Assignees

• Advanced Semiconductor Eng

Inventors

• Appelt Bernd Karl
• Yen You-Lung
• Essig Kay Stefan

Classifications

• H10W72/0198

  batch processes · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W74/114

  by a substrate and the encapsulations · CPC title

• H10W99/00

  Subject matter not provided for in other groups of this subclass · CPC title

• H10W74/014

  using batch processing · CPC title