Addressing layout retargeting shortfalls

Patent metadata

Field	Value
Publication number	US-11574103-B2
Application number	US-202016779179-A
Country	US
Kind code	B2
Filing date	Jan 31, 2020
Priority date	Jan 31, 2020
Publication date	Feb 7, 2023
Grant date	Feb 7, 2023

Abstract

Aspects of the invention provide means for addressing layout retargeting shortfalls. Initially, an original design shape in the layout is allowed to be simulated by process simulation to form process simulation contours. A polygon is then fitted to the process simulation contours to form a fitted simulated shape. Subsequently, whether the fitted simulated shape differs from the original design shape is detected. The process simulation may reflect the changes to the layout that occur at a foundry as part of a retargeting process. Advantageously, addressing a layout for retargeting shortfalls in accordance with aspects of the invention is likely to result in manufactured semiconductor devices having higher yields and reliability than those produced from a like layout that is not addressed in this manner.

First claim

What is claimed is:

1. A method comprising the steps of:
using, using at least one processor, an original design shape in a layout to be simulated by process simulation to form process simulation contours;
fitting, using the at least one processor, a polygon to the process simulation contours to form a fitted simulated shape;
comparing, using the at least one processor, the fitted simulated shape and the original design shape; and
determining, using the at least one processor, whether the fitted simulated shape violates a set of design rules in response to detecting that the fitted simulated shape differs from the original design shape, wherein the fitting step comprises generating a concave hull that characterizes the process simulation contours, fitting a plurality of rectangles to the concave hull and merging the plurality of rectangles to form the polygon.

2. The method of claim 1 , wherein the comparing step comprises comparing the fitted simulated shape to the original design shape utilizing a NOT or an XOR Boolean operation.

3. The method of claim 1 , wherein the determining step comprises determining at least one of width, length, spacing, density, enclosure, or area of the fitted simulated shape.

4. The method of claim 1 , further comprising the step of modifying the layout if the fitted simulated shape violates the set of design rules.

5. The method of claim 4 , wherein the modifying step comprises modifying at least one of size, shape, or position of the original design shape.

6. The method of claim 4 , further comprising the step of manufacturing a semiconductor device based on the modified layout.

7. The method of claim 1 , further comprising providing a system, wherein the system comprises distinct software modules, each of the distinct software modules being embodied on a computer readable storage medium, and wherein:
the distinct software modules comprise a polygon fitting module and a difference detection module;
the fitting step is carried out by the polygon fitting module executing on at least one hardware processor; and
the comparing step is carried out by the difference detection module executing on the at least one hardware processor.

8. An apparatus comprising:
a memory; and
at least one processor coupled to the memory and operative to perform the steps of:
using an original design shape in the layout to be simulated by process simulation to form process simulation contours;
fitting a polygon to the process simulation contours to form a fitted simulated shape;
comparing the fitted simulated shape and the original design shape; and
determining whether the fitted simulated shape violates a set of design rules in response to detecting that the fitted simulated shape differs from the original design shape, wherein the fitting step comprises generating a concave hull that characterizes the process simulation contours, fitting a plurality of rectangles to the concave hull and merging the plurality of rectangles to form the polygon.

9. The apparatus of claim 8 , wherein the comparing step comprises comparing the fitted simulated shape to the original design shape utilizing a NOT or XOR Boolean operation.

10. The apparatus of claim 8 , wherein the determining step comprises determining at least one of width, length, spacing, density, enclosure, or area of the fitted simulated shape.

11. The apparatus of claim 8 , wherein the at least one processor is further operative to perform the step of modifying the layout if the fitted simulated shape violates the set of design rules.

12. The apparatus of claim 11 , wherein the modifying step comprises modifying at least one of size, shape, or position of the original design shape.

13. The apparatus of claim 8 , further comprising a plurality of distinct software modules, each of the distinct software modules being embodied on a computer-readable storage medium, and wherein the distinct software modules comprise a polygon fitting module and a difference detection module, wherein:
the at least one processor is operative to perform the fitting step by executing the polygon fitting module; and
the at least one processor is operative to perform the comparing step by executing the difference detection module.

Assignees

• IBM

Inventors

• Shao Dongbing
• Topaloglu Rasit Onur
• Han Geng
• Cui Yuping

Classifications

• G06F2119/18

  Manufacturability analysis or optimisation for manufacturability · CPC title

• G06F30/392 Primary

  Floor-planning or layout, e.g. partitioning or placement · CPC title

• G06F30/398

  Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] (optical proximity correction [OPC] design processes G03F1/36) · CPC title

• Y02P90/02

  Total factory control, e.g. smart factories, flexible manufacturing systems [FMS] or integrated manufacturing systems [IMS] · CPC title