Current operative analog to digital converter (ADC)

Patent metadata

Field	Value
Publication number	US-11569828-B2
Application number	US-202117503435-A
Country	US
Kind code	B2
Filing date	Oct 18, 2021
Priority date	Nov 8, 2019
Publication date	Jan 31, 2023
Grant date	Jan 31, 2023

Abstract

An analog to digital converter (ADC) senses an analog signal (e.g., a load current) to generate a digital signal. The ADC operates based on a load voltage produced based on charging of an element (e.g., a capacitor) by a load current and a digital to analog converter (DAC) output current (e.g., from a N-bit DAC). The ADC generates a digital output signal representative of a difference between the load voltage and a reference voltage. This digital output signal is used directly, or after digital signal processing, to operate an N-bit DAC to generate a DAC output current that tracks the load current. The digital output signal provided to the N-bit DAC is an inverse function of the load current. The ADC is operative to sense very low currents (e.g., currents as low as is of pico-amps) and consume very little power (e.g., less than 2 μW).

First claim

What is claimed is:

1. An analog to digital converter (ADC) comprising:
an operational amplifier operably coupled to a load, wherein, when enabled, the operational amplifier configured to produce a load voltage based on charging of a feedback capacitor that is operably coupled to an input of the operational amplifier and to an output of the operational amplifier, wherein the input of the operational amplifier is coupled to the load via a single line;
an M-bit analog to digital converter (ADC), wherein when enabled, the M-bit ADC operably coupled and configured to:
receive the load voltage;
receive a reference voltage; and
compare the load voltage to the reference voltage and generate a first digital output signal that is representative of a difference between the load voltage and the reference voltage;

memory that stores operational instructions;
one or more processing modules operably coupled to the M-bit ADC and the memory, wherein, when enabled, the one or more processing modules is configured to execute the operational instructions to process the first digital output signal to generate a second digital output signal that is representative of the difference between the load voltage and the reference voltage, wherein the second digital output signal includes a higher resolution than the first digital output signal; and
an N-bit digital to analog converter (DAC) that is operably coupled to the one or more processing modules, wherein, when enabled, the N-bit DAC operably coupled and configured to generate the DAC output current based on the second digital output signal, the DAC output current tracks the load current, and the load voltage tracks the reference voltage, wherein:
N is a first positive integer;
M is a second positive integer greater than or equal to 1; and
N is greater than M.

2. The ADC of claim 1 , wherein another input of the operational amplifier is grounded.

3. The ADC of claim 1 , wherein:
N is the first positive integer that is less than or equal to 8; and
M is the second positive integer that is greater than or equal to 1 and less than or equal to 4.

4. The ADC of claim 1 , wherein the one or more processing modules, when enabled, is further configured to process the first digital output signal in accordance with performing band pass filtering or low pass filtering to generate the second digital output signal that is representative of the load voltage.

5. The ADC of claim 1 further comprising:
a decimation filter coupled to the one or more processing modules, wherein, when enabled, the decimation filter operably coupled and configured to process the second digital output signal to generate another digital output signal having a lower sampling rate and a higher resolution than the second digital output signal.

6. The ADC of claim 1 further comprising:
a decimation filter coupled to the M-bit ADC, wherein, when enabled, the decimation filter operably coupled and configured to process the first digital output signal to generate another digital output signal having a lower sampling rate and a higher resolution than the first digital output signal.

7. The ADC of claim 1 , wherein the load includes an electrode, a sensor, or a transducer.

8. The ADC of claim 1 , wherein the ADC further configured to provide power to the load.

9. The ADC of claim 1 , wherein the ADC further configured to provide power to the load and simultaneously sense the load voltage.

10. The ADC of claim 1 , wherein:
the load is energized by a source that is different than the ADC; and
the ADC further configured to sense the load voltage without providing power to the load.

11. An analog to digital converter (ADC) comprising:
an operational amplifier operably coupled to a load, wherein, when enabled, the operational amplifier configured to produce a load voltage based on charging of a feedback capacitor that is operably coupled to a first input of the operational amplifier and to an output of the operational amplifier, wherein a second input of the operational amplifier is grounded, wherein the first input of the operational amplifier is coupled to the load via a single line;
an M-bit analog to digital converter (ADC), wherein when enabled, the M-bit ADC operably coupled and configured to:
receive the load voltage;
receive a reference voltage; and
compare the load voltage to the reference voltage and generate a first digital output signal that is representative of a difference between the load voltage and the reference voltage;

memory that stores operational instructions;
one or more processing modules operably coupled to the M-bit ADC and the memory, wherein, when enabled, the one or more processing modules is configured to execute the operational instructions to:
process the first digital output signal to generate a second digital output signal that is representative of the difference between the load voltage and the reference voltage, wherein the second digital output signal includes a higher resolution than the first digital output signal; and
process the first digital output signal in accordance with performing band pass filtering or low pass filtering to generate the second digital output signal that is representative of the load voltage; and

an N-bit digital to analog converter (DAC) that is operably coupled to the one or more processing modules, wherein, when enabled, the N-bit DAC operably coupled and configured to generate the DAC output current based on the second digital output signal, the DAC output current tracks the load current, and the load voltage tracks the reference voltage, wherein:
N is a first positive integer;
M is a second positive integer greater than or equal to 1; and
N is greater than M.

12. The ADC of claim 11 , wherein:
N is the first positive integer that is less than or equal to 8; and
M is the second positive integer that is greater than or equal to 1 and less than or equal to 4.

13. The ADC of claim 11 further comprising:
a decimation filter coupled to the one or more processing modules, wherein, when enabled, the decimation filter operably coupled and configured to process the second digital output signal to generate another digital output signal having a lower sampling rate and a higher resolution than the second digital output signal.

14. The ADC of claim 11 further comprising:
a decimation filter coupled to the M-bit ADC, wherein, when enabled, the decimation filter operably coupled and configured to process the first digital output signal to generate another digital output signal having a lower sampling rate and a higher resolution than the first digital output signal.

15. The ADC of claim 11 , wherein the ADC further configured to provide power to the load and simultaneously sense the load voltage.

16. The ADC of claim 11 , wherein:
the load is energized by a source that is different than the ADC; and
the ADC further configured to sense the load voltage without providing power to the load.

17. An analog to digital converter (ADC) comprising:
an operational amplifier operably coupled to a load, wherein, when enabled, the operational amplifier configured to produce a load voltage based on charging of a feedback capacitor that is operably coupled to a first input of the operational amplifier and to an output of the operational amplifier, wherein a second input of the operational amplifier is grounded, wherein the first input of the operational amplifier is coupled to the load via a single line;
an M-bit analog to digital converter (ADC), wherein when enabled, the M-bit ADC operably coupled and c

Assignees

• Sigmasense Llc

Inventors

• Huynh Phuong

Classifications

• H03M1/462 Primary

  Details of the control circuitry, e.g. of the successive approximation register · CPC title

• H03M1/0626 Primary

  by filtering · CPC title

• H03M3/32

  with special provisions or arrangements for power saving, e.g. by allowing a sleep mode, using lower supply voltage for downstream stages, using multiple clock domains, by selectively turning on stages when needed · CPC title

• H03M1/84

  Non-linear conversion · CPC title

• H03M3/462 Primary

  Details relating to the decimation process (decimation filters in general H03H17/0416, H03H17/0621) · CPC title