Time-domain incremental two-step capacitance-to-digital converter

Patent metadata

Field	Value
Publication number	US-11569826-B2
Application number	US-202117176341-A
Country	US
Kind code	B2
Filing date	Feb 16, 2021
Priority date	Feb 16, 2020
Publication date	Jan 31, 2023
Grant date	Jan 31, 2023

Abstract

An exemplary incremental two-step capacitance-to-digital converter (CDC) with a time-domain sigma-delta modulator (TDΔΣM) includes a voltage-controlled oscillator (VCO)-based integrator that can be used in a low-order loop configuration. Example prototypes are disclosed, which when fabricated in 40-nm CMOS technology, provides CDC resolution of 0.29 fF while dissipating only 0.083 nJ per conversion.

First claim

What is claimed is:

1. A capacitance-to-digital converter (CDC) comprising:
a first stage successive approximation register capacitance-to-digital converter (1 st stage SAR CDC) circuit portion configured to perform a plurality of successive approximations of an input capacitance signal to generate a SAR conversion residue and a first set of converted outputs; and
a second stage time-domain incremental delta-sigma modulator capacitance-to-digital converter (2 nd stage TD incremental ΔΣM CDC) circuit portion that quantizes the SAR conversion residue, using, in part, a voltage-controlled oscillator (VCO) based integrator of the 2 nd stage TD incremental ΔΣM CDC operating in a closed-loop control with a digital-to-analog converted signal generated, in part, by the first set of converted outputs, wherein the 2 nd stage TD incremental ΔΣM CDC generates a second set of converted outputs as a representation of an input sensed capacitance signal, and wherein the VCO integrator provides intrinsic clocked averaging (ICLA) capability that can address mismatches between the digital-to-analog converted signal and the first set of converted outputs.

2. The capacitance-to-digital converter of claim 1 , wherein the 2 nd stage TD incremental ΔΣM CDC circuit portion comprises:
a N-stage ring VCO circuit; and
a phase and frequency detector (PFD) coupled to the N-stage ring VCO circuit to an output for the closed-loop control.

3. The capacitance-to-digital converter of claim 2 , wherein the 2 nd stage TD incremental ΔΣM CDC circuit portion further comprises a passive charge sharing (CS) circuit coupled to the N-stage ring VCO circuit.

4. The capacitance-to-digital converter of claim 2 , wherein the N-stage ring VCO circuit is implemented as a G m -stage-driven current-controlled oscillator (CCO).

5. The capacitance-to-digital converter of claim 4 , wherein the G m -stage-driven CCO is configured to convert the SAR conversion residue into a frequency variation at the output N-stage ring VCO and generate output a phase difference signal.

6. The capacitance-to-digital converter of claim 5 , wherein the PFD is configured to detect and integrate the phase difference signal to generate an integrated phase difference signal.

7. The capacitance-to-digital converter of claim 6 , wherein the PFD comprises a multi-phase quantizer configured to transform the integrated phase difference signal to a multi-level output, the PFD further comprising a sampling circuit to sample the multi-level output.

8. The capacitance-to-digital converter of claim 1 , wherein the closed-loop control comprises a first-order loop.

9. The capacitance-to-digital converter of claim 1 , wherein the 2 nd stage TD incremental ΔΣM CDC is configured to operate in an incremental mode.

10. The capacitance-to-digital converter of claim 1 , wherein the 2 nd stage TD incremental ΔΣM CDC is configured to disable operation during SAR operation of the 1 st stage SAR CDC.

11. The capacitance-to-digital converter of claim 1 , further comprising
a capacitance sensing network circuit coupled to the 1 st stage SAR CDC circuit portion, the capacitance sensing network circuit being configured to switch between a first capacitance sensing input associated with a first capacitive plate and a second capacitance sensing input associated with a second capacitive plate.

12. The capacitance-to-digital converter of claim 11 , wherein the capacitance sensing network circuit comprises a chopper circuit, the chopper circuit being configured to perform the switching between the first capacitance sensing input and the second capacitance sensing input.

13. The capacitance-to-digital converter of claim 6 , wherein the 2 nd stage TD incremental ΔΣM CDC is configured to disable operations during sensing operation of the capacitance sensing network circuit.

14. The capacitance-to-digital converter of claim 1 , wherein the 2 nd stage TD incremental ΔΣM CDC is configured as an N-bit incremental ΔΣM CDC selected from the group consisting of: a 2-bit incremental ΔΣM CDC, a 3-bit incremental ΔΣM CDC, a 4-bit incremental ΔΣM CDC, a 5-bit incremental ΔΣM CDC, a 6-bit incremental ΔΣM CDC, a 7-bit incremental ΔΣM CDC, an 8-bit incremental ΔΣM CDC, a 9-bit incremental ΔΣM CDC, and a 10-bit incremental ΔΣM CDC.

15. The capacitance-to-digital converter of claim 1 , wherein the capacitance-to-digital converter is configured in a microcontroller.

16. The capacitance-to-digital converter of claim 1 , wherein the capacitance-to-digital converter is configured as an integrated chip.

17. A method of converting a sensed capacitance signal, associated with a capacitance source, to an output digital signal representing the sensed capacitance signal, the method comprising:
successively approximating over a first set of plurality of approximations, the sensed capacitance signal to generate i) a residue signal and ii) a first set of converted outputs of the digital signal;
generating a first digital-to-analog converted signal of the first set of converted outputs of the digital signal;
quantizing the residue signal, using, in part, a voltage-controlled oscillator (VCO) based integrator operating in a closed-loop control with a digital-to-analog converted signal generated, in part, by the first set of converted outputs; and
generating a second digital-to-analog converted signal of the second set of converted outputs of the digital signal representing the sensed capacitance signal; and
combining the first digital-to-analog converted signal and second digital-to-analog converted signal to generate a capacitance-to-digital conversion output,
wherein the VCO integrator provides intrinsic clocked averaging (ICLA) capability that can address mismatches between the first digital-to-analog converted signal and the second digital-to-analog converted signal.

18. The method of claim 17 , wherein the quantification operation comprises:
converting the residue signal into a frequency variation to generate an output a phase difference signal;
integrating the phase difference signal to generate an integrated phase difference signal; and
transforming the integrated phase difference signal to a multi-level output for the closed-loop control.

19. The method of claim 17 , wherein the quantization operation is performed via a time-domain sigma-delta modulator (TD ΔΣM).

20. An apparatus comprising:
a first stage successive approximation register capacitance-to-digital converter (1 st stage SAR CDC) circuit portion configured to perform a plurality of successive approximations of an input capacitance signal to generate a SAR conversion residue and a first set of converted outputs; and
a second stage time-domain incremental delta-sigma modulator capacitance-to-digital converter (2 nd stage TD incremental ΔΣM CDC) circuit portion that quantizes the SAR conversion residue, using, in part, a voltage-controlled oscillator (VCO) based integrator of the 2 nd stage TD incremental ΔΣM CDC operating in a closed-loop control with a digital-to-analog converted signal generated, in part, by the first set of converted outputs, wherein the 2 nd stage TD incremental ΔΣM CDC generates a second set of converted outputs as a representation of an input sensed capacitance signal, and wherein the VCO integrator provides intrinsic clocked averaging (ICLA) capability that can address mismatches between the digital-to-analog converted signal and the first set of converted outputs.

Assignees

• Univ Texas

Inventors

• Tang Xiyuan
• Sun Nan

Classifications

• H03M1/002 Primary

  Provisions or arrangements for saving power, e.g. by allowing a sleep mode, using lower supply voltage for downstream stages, using multiple clock domains or by selectively turning on stages when needed · CPC title

• H03M3/458

  Analogue/digital converters using delta-sigma modulation as an intermediate step · CPC title

• H03M1/46

  with digital/analogue converter for supplying reference values to converter · CPC title

• H03M3/34 Primary

  by chopping · CPC title

• H03M1/145

  the steps being performed sequentially in series-connected stages (H03M1/141, H03M1/143, H03M1/16 take precedence) · CPC title