RF switch stack with charge control elements

Patent metadata

Field	Value
Publication number	US-11569812-B2
Application number	US-202016902032-A
Country	US
Kind code	B2
Filing date	Jun 15, 2020
Priority date	Jun 15, 2020
Publication date	Jan 31, 2023
Grant date	Jan 31, 2023

Abstract

Methods and devices to address the undesired DC voltage distribution across switch stacks in OFF state are disclosed. The disclosed devices include charge control elements that sample the RF signal to generate superimposed voltages at specific points of the switch stack biasing circuit. The provided voltages help reducing the drooping voltages on drain/source/body terminals of the transistors within the stack by supplying the current drawn by drain/source terminals of the stacked transistors and/or by sinking the body leakage current exiting the body terminals of such transistors. Methods and techniques teaching how to provide proper tapping points in the biasing circuit to sample the RF signal are also disclosed.

First claim

The invention claimed is:

1. A FET switch stack comprising:
a plurality of field effect transistors (FETs) connected in series; and
a drain-source resistive ladder comprising a plurality of drain-source resistor networks connected in series, each drain-source resistor network connected across a drain and a source of a corresponding FET of the plurality of FETs;
wherein:
the plurality of FETs is connected at one end to a first radio frequency (RF) terminal;
the plurality of FETs comprises a first FET and a second FET, a source terminal of the first FET being connected to a drain terminal of the second FET;
the plurality of drain-source resistor networks comprises a first drain-source resistor network including a serial connection of at least two first drain-source resistors connected to each other at a first tapping point, the serial connection of the at least two first drain-source resistors having a first terminal and a second terminal;
the plurality of drain-source resistor networks further comprises a second drain-source resistor network including a serial connection of at least two second drain-source resistors connected to each other at a second tapping point, the serial connection of the at least two second drain-source resistors having a third terminal and a fourth terminal;
the first terminal is directly connected to a drain terminal of the first FET and the second terminal is directly connected to a source terminal of the first FET;
the third terminal is directly connected to a drain terminal of the second FET and the fourth terminal is directly connected to a source terminal of the second FET;
the FET switch stack further comprising:
one or more drain-source charge control elements comprising a first drain-source charge control element connected to the first tapping point and the second tapping point;
the first drain-source charge control element comprising a first diode connected between the first tapping point and a first charge control resistor and a second diode connected between the second tapping point and a second charge control resistor.

2. The FET switch stack of claim 1 configured to be coupled to an RF signal at the first RF terminal and to use an RF voltage between the first tapping point of the first drain-source resistor network and the second tapping point of the second drain-source resistor network.

3. The FET switch stack of claim 2 , wherein the first drain-source charge control element is configured to use the RF voltage between the first tapping point of the first drain-source resistor network and the second tapping point of the second drain-source resistor network to supply a first current to the source terminal of the first FET and the drain terminal of the second FET.

4. The FET switch stack of claim 1 , wherein:
the first drain-source charge control element comprises a first terminal, a second terminal, and a third terminal, wherein:
an anode of the first diode is connected to the first terminal of the first drain-source charge control element;
the first charge control resistor is connected at one end to a cathode of the first diode and at another end is connected to the third terminal of the first drain-source charge control element:
the first terminal is connected to the first tapping point of the first drain-source resistor network;
the second terminal is connected to the second tapping point of the second drain-source resistor network; and
the third terminal is coupled to the source terminal of the first FET to supply the first current.

5. A FET switch stack comprising:
a plurality of field effect transistors (FETs) connected in series; and
a drain-source resistive ladder comprising a plurality of drain-source resistor networks connected in series, each drain-source resistor network connected across a drain and a source of a corresponding FET of the plurality of FETs;
wherein:
the plurality of FETs is connected at one end to a first radio frequency (RF) terminal;
the plurality of FETs comprises a first FET and a second FET, a source terminal of the first FET being connected to a drain terminal of the second FET;
the plurality of drain-source resistor networks comprises a first drain-source resistor network including a serial connection of at least two first drain-source resistors connected to each other at a first tapping point, the serial connection of the at least two first drain-source resistors having a first terminal and a second terminal;
the plurality of drain-source resistor networks further comprises a second drain-source resistor network including a serial connection of at least two second drain-source resistors connected to each other at a second tapping point, the serial connection of the at least two second drain-source resistors having a third terminal and a fourth terminal;
the first terminal is directly connected to a drain terminal of the first FET and the second terminal is directly connected to a source terminal of the first FET;
the third terminal is directly connected to a drain terminal of the second FET and the fourth terminal is directly connected to a source terminal of the second FET;
the FET switch stack further comprising:
one or more drain-source charge control elements comprising a first drain-source charge control element connected to the first tapping point and the second tapping point and coupled to the source terminal of the first FET and the drain terminal of the second FET;
wherein the first drain-source charge control element comprises a first diode and a first charge control resistor wherein:
an anode of the first diode is connected to the first terminal of the first drain-source charge control element;
the first charge control resistor is connected at one end to a cathode of the first diode and at another end is connected to the third terminal of the first drain-source charge control element.

6. The FET switch stack of claim 5 , wherein:
during an upswing of the RF signal the first diode is conducting; and
during a downswing of the RF signal the first diode is not conducting.

7. The FET switch stack of claim 5 , wherein the first drain-source charge control element further comprises a second diode and a second charge control resistor, wherein:
an anode of the second diode is connected to the second terminal of the first drain-source charge control element;
the second resistor is connected at one end to a cathode of the second diode and at another end is connected to a fourth terminal of the first drain-source charge control element.

8. The FET switch stack of claim 7 , wherein the third terminal is connected to the fourth terminal.

9. The FET switch stack of claim 7 , wherein
during an upswing of the RF signal the first diode is conducting and the second diode is not conducting; and
during a downswing of the RF signal the first diode is not conducting and the second diode is conducting.

10. The FET switch stack of claim 7 , wherein the first drain-source charge control element comprises a first capacitor.

11. The FET switch stack of claim 10 , wherein the first capacitor is configured to be charged during an upswing of the RF signal.

12. The FET switch stack of claim 10 , wherein the first capacitor has a first capacitor end connected to the second terminal of the first drain-source charge control element and a second capacitor end connected to the cathode of the first diode.

13. The FET switch stack of claim 12 , wherein the first drain-source charge control element further comprises a second capacitor connected at one end to the first terminal of the first drain-source charge control element and connected at another end to the ca

Assignees

• Psemi Corp

Inventors

• Shapiro Eric S
• Willard Simon Edward

Classifications

• H03K17/687 Primary

  the devices being field-effect transistors · CPC title

• H03K17/693 Primary

  Switching arrangements with several input- or output-terminals, e.g. multiplexers, distributors (logic circuits H03K19/00; code converters H03M5/00, H03M7/00) · CPC title

• H03K17/6871 Primary

  the output circuit comprising more than one controlled field-effect transistor · CPC title

• H03K2217/0018

  Special modifications or use of the back gate voltage of a FET · CPC title